Sie verwenden einen Browser, in dem JavaScript deaktiviert ist. Dadurch wird verhindert, dass Sie die volle Funktionalität dieser Webseite nutzen können. Zur Navigation müssen Sie daher die Sitemap nutzen.

You are currently using a browser with deactivated JavaScript. There you can't use all the features of this website. In order to navigate the site, please use the Sitemap .

Publications of Rainer Leupers

Publications from Jan/ 2023 to Oct/ 2021

Bosbach, N., Jünger, L., Pelke, R., Zurstraßen, N. and Leupers, R.: Entropy-Based Analysis of Benchmarks for Instruction Set Simulators, in Proceedings of the 2023 Workshop on System Engineering for constrained embedded systems , Jan. 2023, accepted for publication, ISBN: 979-8-40070-045-3, 10.1145/3579170.3579267
Sharma, N. N., Jain , R., Pokkuluri, M. M., Patkar, S., Leupers, R., Nikhil, R. S. and Merchant, F.: CLARINET: A Quire-Enabled RISC-V-Based Framework for Posit Arithmetic Empiricism, in Journal of Systems Architecture (Elsevier), 2023, accepted for publication
Thieu, G. B., Gesper, S., Paya Vaya, G., Riggers, C., Renke, O., Fiedler, T., Marten, J., Stuckenberg, T., Blume, H., Weis, C., Steiner, L., Sudarshan, C., Wehn, N., Reimann, L. M., Leupers, R., Beyer, M., Köhler, D., Jauch, A., Bormann, J. M., Jaberansari, S., Berthold, T., Blawat, M., Kock, M., Schewior, G., Benndorf, J., Kautz, F., Bluethgen, H.-M. and Sauer, C.: ZuSE-KI-AVF: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2023, accepted for publication
Šišejković, D. and Leupers, R.: Logic Locking - A Practical Approach to Secure Hardware, Springer Cham, 1 ed., 2023, ISBN: 978-3-03119-122-0, 10.1007/978-3-031-19123-7
Zurstraßen, N., Jose, C.-C., Joseph, J. M., Leupers, R., Xinghua, X. and Yichao, L.: par-gem5: Parallelizing gem5 s Atomic Mode, in 2023 Design, Automation and Test in Europe Conference (DATE), 2023, accepted for publication
Reimann, L. M., Erdonmez, S., Šišejković, D. and Leupers, R.: Quantitative Information Flow for Hardware: Advancing the Attack Landscape, in LASCAS 2023, Nov. 2022, accepted for publication, 10.48550/arXiv.2211.16891
Birke, S., Hartmann, B., Auras, D., Wloka, M., Ascheid, G. and Leupers, R.: Design and Exploration of an ARC-Coprocessor for LSTM Based Audio Applications, in 2022 IEEE Nordic Circuits and Systems Conference (NorCAS) , Oct. 2022, 10.1109/NorCAS57515.2022.9934553 ©2022 IEEE
Singh, S., Bodapati, S., Patkar, S., Leupers, R., Chattopadhyay, A. and Merchant, F.: PA-PUF: A Novel Priority Arbiter PUF, in VLSI-SoC, Oct. 2022, accepted for publication ©2022 IEEE
Moussavi, E., Šišejković, D., Singh, A., Kizatov, D., Leupers, R., Ingebrandt, S., Pachauri, V. and Merchant, F.: A Temperature Independent Readout Circuit for ISFET-Based Sensor Application, in 2022 IEEE 23rd Latin American Test Symposium (LATS), pp. 1-4, Sep. 2022, 10.1109/LATS57337.2022.9937020
Moussavi, E., Šišejković, D., Brings, F., Kizatov, D., Singh, A., Xuan , T. V., Ingebrandt, S., Leupers, R., Pachauri, V. and Merchant, F.: pHGen: A pH-Based Key Generation Mechanism Using ISFETs, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 61-64, Jun. 2022, 10.1109/HOST54066.2022.9840282 ©2022 IEEE
Galicia, M., Merchant, F. and Leupers, R.: A Parallel SystemC Virtual Platform for Neuromorphic Architectures, in International Symposium on Quality Electronic Design (ISQED) 2022, Apr. 2022, 10.1109/ISQED54688.2022.9806235 ©2022 IEEE
Staudigl, F., Al Indari, H., Schön, D., Šišejković, D., Merchant, F., Joseph, J. M., Rana, V., Menzel, S. and Leupers, R.: NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, 10.23919/DATE54114.2022.9774651 ©2022 IEEE
Galicia, M., Menzel, S., Merchant, F., Müller, M., Chen, H.-Y. , Zhao, Q.-T. , Cüppers, F. , Jalil, A. R. , Shu, Q. , Schüffelgen, P., Mussler, G., Funck, C. , Lanius, C. , Wiefels, S. , von Witzleben, M. , Bengel, C. , Kopperberg, N. , Ziegler, T. , Walied, R. , Krüger, A. , Pöhls, L. , Dittmann, R. , Hoffmann-Eifert, S. , Rana, V., Grützmacher, D. , Wuttig, M. , Wouters, D. , Vescan, A. , Gemmeke, T. , Knoch, J. , Lemme, M. , Leupers, R. and Waser, R.: NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, 10.23919/DATE54114.2022.9774755 ©2022 IEEE
Šišejković, D., Collini, L., Tan, B., Pilato, C., Karri, R. and Leupers, R.: Designing ML-Resilient Locking at Register-Transfer Level, in 59th ACM/EDAC/IEEE Design Automation Conference (DAC), p. 769–774, Association for Computing Machinery, 2022, ISBN: 978-1-45039-142-9, 10.1145/3489517.3530541 ©2022 IEEE
Bosbach, N., Jünger, L., Joseph, J. M. and Leupers, R.: NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool, in 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC) , IEEE, 2022, ISBN: 978-1-66549-006-1, ISSN: 2324-8440, 10.1109/VLSI-SoC54400.2022.9939578 ©2022 IEEE
Staudigl, F., Sturm, K. J. X., Bartel, M., Fetz, T., Šišejković, D., Joseph, J. M., Bolzani Pöhls, L. and Leupers, R.: X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation, in International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, accepted for publication ©2022 IEEE
Birke, S., Hartmann, B., Auras, D., Wloka, M., Ascheid, G. and Leupers, R.: Design and Exploration of an ARC-Coprocessor for LSTM Based Audio Applications, in 2022 IEEE Nordic Circuits and Systems Conference (NorCAS), pp. 1-7, 2022, 10.1109/NorCAS57515.2022.9934553 ©2022 IEEE
Zurstraßen, N., Jünger, L., Kogel, T., Keding, H. and Leupers, R.: AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators, in International Journal of Parallel Programming, 2022, 10.1007/s10766-022-00728-3
Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.: QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog, in Proceedings of the International Conference on Computer Design (ICCD) , pp. 603-607, Oct. 2021, 10.1109/ICCD53106.2021.00097 ©2021 IEEE
Joseph, J. M., Baloglu, M. S. , Pan, Y., Leupers, R. and Bamberg, L.: NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI, in NOCS '21: Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip, p. 15–20, Oct. 2021, 10.1145/3479876.3481591

Code Optimization Techniques for Embedded Processors - Methods, Algorithms, and Tools

Retargetable Compiler Technology for Embedded Systems - Tools and Applications

Retargetable Code Generation for Digital Signal Processors