Publications of Rainer Leupers

Publications from Jun/ 2006 to Mar/ 2005

• Kogel, T., Leupers, R. and Meyr, H.: Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms, Springer, Jun. 2006, ISBN: 1-402-04825-4, 10.1007/1-4020-4826-2
  
• Ceng, J., Sheng, W., Hohenauer, M., Leupers, R., Ascheid, G. and Meyr, H.: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting, in Journal of VLSI Signal Processing, Vol. 43, No. 2-3, pp. 235-246, Jun. 2006
  
• Chattopadhyay, A., Sinha, A., Zhang, D., Leupers, R., Ascheid, G. and Meyr, H.: Integrated Verification Approach during ADL-driven Processor Design, in IEEE International Workshop on Rapid System Prototyping (RSP)(Chania, Crete), in IEEE International Workshop on Rapid System Prototyping (RSP)(Chania, Crete), Jun. 2006
  
• Chattopadhyay, A., Kammler, D., Witte, E. M., Schliebusch, O., Ishebabi, H., Geukes, G., Leupers, R., Ascheid, G. and Meyr, H.: Automatic Low Power Optimizations during ADL-driven ASIP Design, in Proceedings of the International Symposium on VLSI Design, Automation & Test (VLSI-DAT)(Hsinchu, Taiwan), pp. 123--126, Apr. 2006
  
• Kempf, T., Karuri, K., Wallentowitz, S., Ascheid, G., Leupers, R. and Meyr, H.: A SW performance estimation framework for early System-Level-Design using fine-grained instrumentation, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
  
• Chattopadhyay, A., Geukes, B., Kammler, D., Witte, E. M., Schliebusch, O., Ishebabi, H., Leupers, R., Ascheid, G. and Meyr, H.: Automatic ADL-based Operand Isolation for Embedded Processors, in Design, Automation & Test in Europe (DATE)(Munich, Germany), pp. 600--605, Mar. 2006
  
• Leupers, R., Karuri, K., Kraemer, S. and Pandey, M.: A Design Flow for Configurable Embedded Processors based on Optimized Instruction Set Extension Synthesis, in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
  
• Karuri, K., Leupers, R., Ascheid, G., Meyr, H. and Kedia, M.: Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
  
• Fanucci, L., Cassiano, M., Saponara, S., Kammler, D., Witte, E. M., Schliebusch, O., Ascheid, G., Leupers, R. and Meyr, H.: ASIP Design and Synthesis for Non Linear Filtering in Image Processing, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Munich, Germany), pp. 233--238, Mar. 2006
  
• Angiolini, F., Ceng, J., Leupers, R., Ferrari, F., Ferri, C. and Benini, L.: An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration, in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
  
• Scharwächter, H., Hohenauer, M., Leupers, R., Ascheid, G. and Meyr, H.: An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
  
• Leupers, R., Hohenauer, M., Karuri, K., Braun, G., Ceng, J., Scharwächter, H., Ascheid, G. and Meyr, H.: Retargetable Compilers and Architecture Exploration for Embedded Processors, in System On Chip: Next Generation Electronics, 2006
  
• Witte, E. M., Chattopadhyay, A., Schliebusch, O., Kammler, D., Leupers, R., Ascheid, G. and Meyr, H.: Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation, in Proceedings of the International Conference on Computer Design (ICCD)(San Jose, California, USA), pp. 193--199, Oct. 2005
  
• Wieferink, A., Michiels, T., Nohl, A., Kogel, T., Leupers, R., Ascheid, G. and Meyr, H.: Retargetable Generation of TLM Bus Interfaces for MP-SoC Platforms, in 3rd IEEE/ACM/IFIP International Conference on HW/SW Codesign and System Synthesis (CODES+ISSS)(Jersey City, NJ, USA), in 3rd IEEE/ACM/IFIP International Conference on HW/SW Codesign and System Synthesis (CODES+ISSS)(Jersey City, NJ, USA), Sep. 2005
  
• Mozumdar, M., Karuri, K., Chattopadhyay, A., Kraemer, S., Scharwächter, H., Meyr, H., Ascheid, G. and Leupers, R.: Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study, in IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)(Samos, Greece), Jul. 2005
  
• Schliebusch, O., Chattopadhyay, A., Witte, E. M., Kammler, D., Ascheid, G., Leupers, R. and Meyr, H.: Optimization Techniques for ADL-driven RTL Processor Synthesis, in Proceedings of the IEEE International Workshop on Rapid Systems Prototyping (RSP)(Montreal, Canada), pp. 165--171, Jun. 2005
  
• Karuri, K., Al Faruque, M. A., Kraemer, S., Leupers, R., Ascheid, G. and Meyr, H.: Fine-grained Application Source Code Profiling for ASIP Design, in 42nd Design Automation Conference(Anaheim, California, USA), Jun. 2005
  
• Schliebusch, O., Ascheid, G., Wieferink, A., Leupers, R. and Meyr, H.: Application Specific Processors for Flexible Receivers, in Proc. of National Symposium of Radio Science (URSI)(Poznan (Poland)), in Proc. of National Symposium of Radio Science (URSI)(Poznan (Poland)), Apr. 2005
  
• Kempf, T., Dörper, M., Leupers, R., Ascheid, G., Meyr, H., Kogel, T. and Vanthournout, B.: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2005
  
• Ceng, J., Hohenauer, M., Leupers, R., Ascheid, G., Meyr, H. and Braun, G.: C Compiler Retargeting Based on Instruction Semantics Models., in DATE(Munich, Germany), in DATE(Munich, Germany), Mar. 2005
  

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