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Publications of Rainer Leupers

Publications from Jun/ 2024 to 2023

Bosbach, N., Zurstraßen, N., Pelke, R., Jünger, L., Weinstock, J. H. and Leupers, R.: Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models, in Design Automation Conference , Jun. 2024, accepted for publication, 10.1145/3649329.3658257
Reimann, L. M., Prashar, A., Ghinami, C., Pelke, R., Šišejković, D., Merchant, F. and Leupers, R.: QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL, in Proceedings of the International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Apr. 2024
Bosbach, N., Salama, A., Jünger, L., Burton, M., Zurstraßen, N., Pelke, R. and Leupers, R.: NQC²: A Non-Intrusive QEMU Code Coverage Plugin, in Rapid Simulation and Performance Evaluation for Design (RAPIDO '24), January 18, 2024, Munich, Germany ( New York, NY, USA), Association for Computing Machinery, Jan. 2024, ISBN: 979-8-40071-791-8, 10.1145/3642921.3642924
Zurstraßen, N., Brandhofer, R., Cubero-Cascante, J., Bosbach, N., Jünger, L. and Leupers, R.: The Optimal Quantum of Temporal Decoupling, in 29th Asia and South Pacific Design Automation Conference, 2024, 10.1109/ASP-DAC58780.2024.10473967 ©2024 IEEE
Pelke, R., Cubero-Cascante, J., Bosbach, N., Staudigl, F., Leupers, R. and Joseph, J. M.: CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2024, accepted for publication, 10.48550/arXiv.2401.07671 ©2024 IEEE
Cubero-Cascante, J., Vaidyanathan, A., Pelke, R., Pfeifer, L., Leupers, R. and Joseph, J. M.: A Calibratable Model for Fast Energy Estimation of MVM Operations on RRAM Crossbars, in 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), pp. 537-541, 2024, accepted for publication
Reimann, L. M., Madhukumar Variyar, Y., Huelser, L., Ghinami, C., Germek, D. and Leupers, R.: Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction, in Philosophical Transactions of the Royal Society A, 2024, accepted for publication, 10.1098/rsta.2023.0388
Reimann, L. M., Wiesner, J., Jaszczyk, K., Germek, D., Merchant, F. and Leupers, R.: Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow's Advanced Memory Range Feature, in Springer Nature, Vol. VLSI-SoC 2023: Silicon Innovations for Trustworthy Artificial Intelligence, 2024, accepted for publication
Happek, L., Huang, J., Gener, A. G., Leupers, R. and Galicia, M.: Spiking Neural Networks for Signal Classification with Digital and Analog Neuromorphic Systems: A Comparative Study, in 2024 International Joint Conference on Neural Networks (IJCNN), pp. 1-7, 2024, 10.1109/IJCNN60899.2024.10650824
Reimann, L. M., Wiesner, J., Šišejković, D., Merchant, F. and Leupers, R.: SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors, in 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Oct. 2023, 10.1109/VLSI-SoC57769.2023.10321922 ©2023 IEEE
Pelke, R., Bosbach, N., Cubero-Cascante, J., Staudigl, F., Leupers, R. and Joseph, J. M.: Mapping of CNNs on multi-core RRAM-based CIM architectures, in 2023 IFIP/IEEE 31th International Conference on Very Large Scale Integration (VLSI-SoC) , Oct. 2023, 10.48550/arXiv.2309.03805 ©2023 IEEE
Bosbach, N., Pelke, R., Zurstraßen, N., Jünger, L., Weinstock, J. H. and Leupers, R.: Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TLM-2.0-based Virtual Platforms, in International Conference on Hardware/Software Codesign and System Synthesis , Sep. 2023, 10.1145/3607888.3608596
Galicia, M., Osman, I., Owusu-Afriyie, C. and Leupers, R.: "S3cure": Scramble, Shuffle and Shambles - Secure Deployment of Weight Matrices in Memristor Crossbar Arrays, in Association for Computing Machinery, ACM, ICONS '23: Proceedings of the 2023 International Conference on Neuromorphic Systems, Aug. 2023, 10.1145/3589737.3605964
Reimann, L. M., Staudigl, F. and Leupers, R.: Automated Information Flow Analysis for Integrated Computing-in-Memory Modules, in IEEE NEWCAS, Jun. 2023, 10.1109/NEWCAS57931.2023.10198075 ©2023 IEEE
Moussavi, E., Singh, A., Šišejković, D., Kumar, A., Kizatov, D., Ingebrandt, S., Leupers, R., Pachauri, V. and Merchant, F.: Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic, in arXiv preprint arXiv:2304.05686, The 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023) , Jun. 2023, accepted for publication, 10.48550/arXiv.2304.05686 ©2023 IEEE
Galicia, M., Happek, L., Balzer, M. and Leupers, R.: Frequency and noise characterization for baseband signal processing on neuromorphic circuits, in 21st IEEE Interregional NEWCAS Conference (NEWCAS), Jun. 2023, 10.1109/NEWCAS57931.2023.10198095 ©2023 IEEE
Bosbach, N., Jünger, L., Pelke, R., Zurstraßen, N. and Leupers, R.: Entropy-Based Analysis of Benchmarks for Instruction Set Simulators, in RAPIDO2023: Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems (New York, NY, USA), pp. 54-59, Association for Computing Machinery, Jan. 2023, ISBN: 979-8-40070-045-3, 10.1145/3579170.3579267
Sharma, N. N., Jain , R., Pokkuluri, M. M., Patkar, S., Leupers, R., Nikhil, R. S. and Merchant, F.: CLARINET: A Quire-Enabled RISC-V-Based Framework for Posit Arithmetic Empiricism, in Journal of Systems Architecture (Elsevier), 2023, accepted for publication
Thieu, G. B., Gesper, S., Paya Vaya, G., Riggers, C., Renke, O., Fiedler, T., Marten, J., Stuckenberg, T., Blume, H., Weis, C., Steiner, L., Sudarshan, C., Wehn, N., Reimann, L. M., Leupers, R., Beyer, M., Köhler, D., Jauch, A., Bormann, J. M., Jaberansari, S., Berthold, T., Blawat, M., Kock, M., Schewior, G., Benndorf, J., Kautz, F., Bluethgen, H.-M. and Sauer, C.: ZuSE-KI-AVF: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2023
Šišejković, D. and Leupers, R.: Logic Locking - A Practical Approach to Secure Hardware, Springer Cham, 1 ed., 2023, ISBN: 978-3-03119-122-0, 10.1007/978-3-031-19123-7

Code Optimization Techniques for Embedded Processors - Methods, Algorithms, and Tools

Retargetable Compiler Technology for Embedded Systems - Tools and Applications

Retargetable Code Generation for Digital Signal Processors