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QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL

Authors:: Reimann, L. M. , Prashar, A. , Ghinami, C. , Pelke, R. , Šišejković, D. , Merchant, F. , Leupers, R.
Book Title:: Proceedings of the International Symposium on VLSI Design, Automation & Test (VLSI-DAT)
Status:: accepted for publication
Date:: Apr. 2024
Language:: English
Abstract:: In contemporary Electronic Design Automation tools, security often takes a backseat to the primary goals of power, performance, and area optimization. Commonly, the security analysis is conducted by hand, leading to vulnerabilities in the design remaining unnoticed. Security-aware EDA tools assist the designer in the identification and removal of security threats while keeping performance and area in mind. Cutting-edge methods employ information flow analysis to identify inadvertent information leaks in design structures. Current information leakage detection methods use quantitative information flow analysis to quantify the leaks. However, handling sequential circuits poses challenges for state-of-the-art techniques due to their time-agnostic nature, overlooking timing channels, and introducing false positives. To address this, we introduce QTFlow, a timing-sensitive framework for quantifying hardware information leakages during the design phase.
Illustrating its effectiveness on open-source benchmarks, QTFlow autonomously identifies timing channels and diminishes all false positives arising from time-agnostic analysis when contrasted with current state-of-the-art techniques.
Download:: BibTeX