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Dr.-Ing. Dominik Šišejković

Postdoctoral Researcher

Room: 504
+49 241 80-28302
+49 241 80-28306
dominik.sisejkovic(at)ice.rwth-aachen.de
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Biography

Dominik Šišejković received the B.Sc. and M.Sc. degree in software engineering from the Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia, in 2014 and 2016, respectively. In February 2022, he defended the Ph.D. (Dr.-Ing.) thesis at the Faculty of Electrical Engineering and Information Technology, RWTH Aachen University with the grade "summa cum laude" (with the highest honor). From Sep/2016 to Feb/2022 he worked as a research assistant at the Institute for Communication Technologies and Embedded Systems. From Sep/2017 to Feb/2022, he worked as Technical Project Officer of the EU-funded project TETRAMAX; facilitating technology transfer from academia to European SMEs. From Oct/2018 to June/2022, he was the Chief Engineer of the Chair for Software for Systems on Silicon. Since Feb/2022, he has been working as a postdoctoral researcher at the Institute for Communication Technologies and Embedded Systems. Since 2019, he has co-organized the annual SeHAS workshop on secure hardware, architectures and operating systems at the HiPEAC conference. Since 2020, he has been part of the technical committee for the hardware and systems security track at the International Symposium on Quality Electronic Design (ISQED).

For his doctoral work, he contributed to various aspects of logic locking (a hardware protection methodology), thereby focusing on preventing malicious design modifications (hardware Trojans) within hardware designs. In addition, he was directly involved in the design and implementation of the logic-locking framework that was applied for the production of the first logic-locked RISC-V processor core on the market.

Awards

Best Ph.D award at the IFIP/IEEE VLSI-SoC conference (2021).
ICT Young Researcher Award by RWTH Aachen University for significant contributions in the ICT research area (2020).
HiPEAC Technology Transfer Award for successfully transferring a scalable logic-locking framework for hardware integrity protection to the industry (2020).

Projects

Tools Projects:
- Hardware Security: Secure Processor Design
Collaborative projects:

Research Interest

Hardware Security
Security-Aware Electronic Design Automation (EDA)
Secure Processor Design
Embedded Systems
Machine Learning for Security

Teaching

Thesis & Student Jobs

Students interested in a BSc/MSc thesis or a HiWi job are asked to make an appointment via email to personally visit the institute. Open positions can be found here.

Publications

Publications from Sep/ 2022 to Sep/ 2018

Moussavi, E., Šišejković, D., Singh, A., Kizatov, D., Leupers, R., Ingebrandt, S., Pachauri, V. and Merchant, F.: A Temperature Independent Readout Circuit for ISFET-Based Sensor Application, in IEEE LATS, Sep. 2022, accepted for publication
Moussavi, E., Šišejković, D., Brings, F., Kizatov, D., Singh, A., Xuan , T. V., Ingebrandt, S., Leupers, R., Pachauri, V. and Merchant, F.: pHGen: A pH-Based Key Generation Mechanism Using ISFETs, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Jun. 2022, accepted for publication ©2022 IEEE
Staudigl, F., Al Indari, H., Schön, D., Šišejković, D., Merchant, F., Joseph, J. M., Rana, V., Menzel, S. and Leupers, R.: NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, 10.23919/DATE54114.2022.9774651 ©2022 IEEE
Šišejković, D.: Designing Trustworthy Hardware with Logic Locking, Ph. D. Dissertation RWTH Aachen Univeristy, Mar. 2022, 10.18154/RWTH-2022-02625
Šišejković, D., Collini, L., Tan, B., Pilato, C., Karri, R. and Leupers, R.: Designing ML-Resilient Locking at Register-Transfer Level, in 59th ACM/EDAC/IEEE Design Automation Conference (DAC), 2022, accepted for publication ©2022 IEEE
Staudigl, F., Sturm, K. J. X., Bartel, M., Fetz, T., Šišejković, D., Joseph, J. M., Bolzani Pöhls, L. and Leupers, R.: X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation, in International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, accepted for publication ©2022 IEEE
Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.: QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog, in Proceedings of the International Conference on Computer Design (ICCD) , pp. 603-607, Oct. 2021, 10.1109/ICCD53106.2021.00097 ©2021 IEEE
Šišejković, D., Merchant, F., Reimann, L. M. and Leupers, R.: Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Jul. 2021, ISSN: 1937-4151, 10.1109/TCAD.2021.3100275 ©2021 IEEE
Šišejković, D., Merchant, F., Reimann, L. M., Srivastava, H., Hallawa, A. and Leupers, R.: Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach, in ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 17, Association for Computing Machinery, p. 26, May. 2021, ISSN: 1550-4832, 10.1145/3431389
Rai, S., Garg, S., Pilato, C., Herdt, V., Moussavi, E., Šišejković, D., Karri, R., Drechsler, R., Merchant, F. and Kumar, A.: Vertical IP Protection of the Next-Generation Devices: Quo Vadis?, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, 10.23919/DATE51398.2021.9474132
Merchant, F., Šišejković, D., Reimann, L. M., Yasotharan, K., Grass, T. and Leupers, R.: ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework, in Proceedings of the International Conference on VLSI Design (VLSID), 2021, 10.1109/VLSID51830.2021.00051 ©2021 IEEE
Šišejković, D., Reimann, L. M., Moussavi, E., Merchant, F. and Leupers, R.: Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities, in IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), 2021, 10.1109/VLSI-SoC53125.2021.9606979 ©2021 IEEE
Šišejković, D. and Leupers, R.: Trustworthy Hardware Design with Logic Locking, in IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), IEEE, 2021, 10.1109/VLSI-SoC53125.2021.9606998 ©2021 IEEE
Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R. and Kegreiß, S.: Scaling Logic Locking Schemes to Multi-Module Hardware Designs, in Architecture of Computing Systems (ARCS 2020), Springer International Publishing, pp. 138--152, 2020, 10.1007/978-3-030-52794-5_11 ©2020 IEEE
Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R., Giacometti, M. and Kegreiß, S.: A Secure Hardware-Software Solution Based on RISC-V, Logic Locking and Microkernel, in Proceedings of the 23nd International Workshop on Software and Compilers for Embedded Systems (SCOPES), p. 62–65, Association for Computing Machinery, 2020, 10.1145/3378678.3391886 ©2020 IEEE
Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 2019 IEEE European Test Symposium (ETS), pp. 1-6, May. 2019, ISSN: 1530-1877, 10.1109/ETS.2019.8791528 ©2019 IEEE
Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE
Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), IEEE, p. 4, Apr. 2019, 10.1109/VLSI-DAT.2019.8741531 ©2019 IEEE
Šišejković, D., Merchant, F. and Leupers, R.: Protecting the Integrity of Processor Cores with Logic Encryption, in 2019 32nd IEEE International System-on-Chip Conference (SOCC), pp. 424-425, 2019, 10.1109/SOCC46988.2019.1570564157 ©2019 IEEE
Đumić, M., Šišejković, D., Čorić , R. and Jakobović, D.: Evolving Priority Rules for the Resource Constrained Project Scheduling Problem with Genetic Programming, in Future Generation Computer Systems, Vol. 86, pp. 211 - 221, Sep. 2018, ISSN: 0167-739X, 10.1016/j.future.2018.04.029

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Felix Staudigl