Farhad Merchant

Publications from 2020 to 2014

Guntoro, A., De La Parra, C., Merchant, F., De Dinechin, F., Gustafson, J. L., Langhammer, M., Leupers, R. and Sangeeth, N.: Next Generation Arithmetic for Edge Computing, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2020, accepted for publication

Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R. and Kegreiß, S.: Scaling Logic Locking Schemes to Multi-Module Hardware Designs, in Architecture of Computing Systems -- ARCS 2020, Springer International Publishing, 2020, accepted for publication ©2020 IEEE

Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R., Giacometti, M. and Kegreiß, S.: A Secure Hardware-Software Solution Based on RISC-V, Logic Locking and Microkernel, in Proceedings of the 23nd International Workshop on Software and Compilers for Embedded Systems, p. 62–65, Association for Computing Machinery, 2020, 10.1145/3378678.3391886 ©2020 IEEE

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 2019 IEEE European Test Symposium (ETS), pp. 1-6, May. 2019, ISSN: 1530-1877, 10.1109/ETS.2019.8791528 ©2019 IEEE

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), IEEE, p. 4, Apr. 2019, 10.1109/VLSI-DAT.2019.8741531 ©2019 IEEE

Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: Applying Modified Householder Transform to Kalman Filter, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019, 10.1109/VLSID.2019.00092

Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-design, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019

Šišejković, D., Merchant, F. and Leupers, R.: Protecting the Integrity of Processor Cores with Logic Encryption, in 2019 32nd IEEE International System-on-Chip Conference (SOCC), pp. 424-425, 2019, 10.1109/SOCC46988.2019.1570564157 ©2019 IEEE

Chaurasiya, R., John, G., Shrestha, R., Jonathan, N., Sangeeth, N., Kaustav, N., Merchant, F. and Leupers, R.: Parameterized Posit Arithmetic Hardware Generator, in Proceedings of the International Conference on Computer Design (ICCD), pp. 334-341, Oct. 2018, 10.1109/ICCD.2018.00057 ©2018 IEEE

Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design, in Applied Reconfigurable Computing, May. 2018, 10.1007/978-3-319-78890-6

Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization, in IEEE Transactions on Parallel and Distributed Systems, IEEE, Mar. 2018, 10.1109/TPDS.2018.2803820 ©2018 IEEE

Merchant, F., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design, in Parallel Processing Letters, Vol. 27, No. 03n04, World Scientific, pp. 1--17, Dec. 2017, 10.1142/S0129626417500062

Bhattacharjee, D., Merchant, F. and Chattopadhyay, A.: Enabling in-memory computation of binary {BLAS} using ReRAM crossbar arrays, in VLSI-SoC, Sep. 2016, ISBN: 978-1-50903-561-8, 10.1109/VLSI-SoC.2016.7753568 ©2016 IEEE

Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation, in VLSI Design, pp. 98--103, 2016, ISBN: 978-1-46738-700-2, 10.1109/VLSID.2016.109 ©2016 IEEE

Merchant, F., Nimash, C., Nandy, S. K. and Narayan, R.: Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic, in VLSI Design, pp. 415--420, 2016, ISBN: 978-1-46738-700-2, 10.1109/VLSID.2016.113 ©2016 IEEE

Merchant, F., Maity, A., Mahadurkar,, M., Vatwani, K., Munje, I., Krishna C, M., Sivanandan, N., Gopalan, N., Raha, S., Nandy, S. K. and Narayan, R.: Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations, in VLSI Design, pp. 153--158, 2015, ISBN: 978-1-47996-658-5, 10.1109/VLSID.2015.31 ©2015 IEEE

Rákossy, Z. E., Merchant, F., Acosta Aponte, A., Nandy, S. K. and Chattopadhyay, A.: Scalable and Energy-Efficient Reconfigurable Accelerator for Column-Wise Givens Rotation, in 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)(Playa-del-Carmen, Mexico), IEEE, Oct. 2014, 10.1109/VLSI-SoC.2014.7004166 ©2014 IEEE

Rákossy, Z. E., Merchant, F., Acosta Aponte, A., Nandy, S. K. and Chattopadhyay, A.: Efficient and Scalable CGRA-based Implementation of Column-wise Givens Rotation, in 25th IEEE International Conference on Application-specific Systems, Architectures and Processors(Zuerich, Switzerland), Jun. 2014, 10.1109/ASAP.2014.6868659 ©2014 IEEE

Merchant, F., Chattopadhyay, A., Garga, G., Nandy, S. K. and Narajan, R.: Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR) , in 27th International Conference on VLSI Design, IIT Bombay, Mumbai India January 7-9, pp. 258 - 263 , 2014, ISSN: 1063-9667, 10.1109/VLSID.2014.51 ©2014 IEEE

>>