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Alumni Postdoctoral Researcher Farhad Merchant

Publications

Publications from Oct/ 2023 to 2021

Reimann, L. M., Wiesner, J., Šišejković, D., Merchant, F. and Leupers, R.: SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors, in 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Oct. 2023, accepted for publication
Moussavi, E., Singh, A., Šišejković, D., Kumar, A., Kizatov, D., Ingebrandt, S., Leupers, R., Pachauri, V. and Merchant, F.: Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic, in arXiv preprint arXiv:2304.05686, The 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023) , Jun. 2023, accepted for publication, 10.48550/arXiv.2304.05686 ©2023 IEEE
Raj, A., Avula, N., Das, P., Šišejković, D., Merchant, F. and Acharyya, A.: DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Jan. 2023, accepted for publication
Singh, S., Zahoor, F., Rajendran, G., Patkar, S., Chattopadhyay, A. and Merchant, F.: Hardware Security Primitives using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs, in ASP-DAC 2023, 2023, accepted for publication ©2023 IEEE
Sharma, N. N., Jain , R., Pokkuluri, M. M., Patkar, S., Leupers, R., Nikhil, R. S. and Merchant, F.: CLARINET: A Quire-Enabled RISC-V-Based Framework for Posit Arithmetic Empiricism, in Journal of Systems Architecture (Elsevier), 2023, accepted for publication
Singh, S., Bodapati, S., Patkar, S., Leupers, R., Chattopadhyay, A. and Merchant, F.: PA-PUF: A Novel Priority Arbiter PUF, in VLSI-SoC, Oct. 2022, accepted for publication ©2022 IEEE
Moussavi, E., Šišejković, D., Singh, A., Kizatov, D., Leupers, R., Ingebrandt, S., Pachauri, V. and Merchant, F.: A Temperature Independent Readout Circuit for ISFET-Based Sensor Application, in 2022 IEEE 23rd Latin American Test Symposium (LATS), pp. 1-4, Sep. 2022, 10.1109/LATS57337.2022.9937020
Merchant, F.: Security as an Important Ingredient in Neuromorphic Engineering, in IEEE ISVLSI, pp. 314-319, Jul. 2022, 10.1109/ISVLSI54635.2022.00068 ©2022 IEEE
Moussavi, E., Šišejković, D., Brings, F., Kizatov, D., Singh, A., Xuan , T. V., Ingebrandt, S., Leupers, R., Pachauri, V. and Merchant, F.: pHGen: A pH-Based Key Generation Mechanism Using ISFETs, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 61-64, Jun. 2022, 10.1109/HOST54066.2022.9840282 ©2022 IEEE
Gansen, M., Lou, J., Freye, F., Gemmeke, T. , Merchant, F., Zeyer, A., Zeineldeen, M., Schlüter, R. and Fan, X.: Discrete Steps towards Approximate Computing, in ISQED , Apr. 2022, 10.1109/ISQED54688.2022.9806215 ©2022 IEEE
Galicia, M., Merchant, F. and Leupers, R.: A Parallel SystemC Virtual Platform for Neuromorphic Architectures, in International Symposium on Quality Electronic Design (ISQED) 2022, Apr. 2022, 10.1109/ISQED54688.2022.9806235 ©2022 IEEE
Staudigl, F., Al Indari, H., Schön, D., Šišejković, D., Merchant, F., Joseph, J. M., Rana, V., Menzel, S. and Leupers, R.: NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, 10.23919/DATE54114.2022.9774651 ©2022 IEEE
Galicia, M., Menzel, S., Merchant, F., Müller, M., Chen, H.-Y. , Zhao, Q.-T. , Cüppers, F. , Jalil, A. R. , Shu, Q. , Schüffelgen, P., Mussler, G., Funck, C. , Lanius, C. , Wiefels, S. , von Witzleben, M. , Bengel, C. , Kopperberg, N. , Ziegler, T. , Walied, R. , Krüger, A. , Pöhls, L. , Dittmann, R. , Hoffmann-Eifert, S. , Rana, V., Grützmacher, D. , Wuttig, M. , Wouters, D. , Vescan, A. , Gemmeke, T. , Knoch, J. , Lemme, M. , Leupers, R. and Waser, R.: NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, 10.23919/DATE54114.2022.9774755 ©2022 IEEE
Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.: QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog, in Proceedings of the International Conference on Computer Design (ICCD) , pp. 603-607, Oct. 2021, 10.1109/ICCD53106.2021.00097 ©2021 IEEE
Staudigl, F., Merchant, F. and Leupers, R.: A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators and Security, in IEEE Design & Test, Sep. 2021, 10.1109/MDAT.2021.3102013 ©2021 IEEE
Šišejković, D., Merchant, F., Reimann, L. M. and Leupers, R.: Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Jul. 2021, ISSN: 1937-4151, 10.1109/TCAD.2021.3100275 ©2021 IEEE
Šišejković, D., Merchant, F., Reimann, L. M., Srivastava, H., Hallawa, A. and Leupers, R.: Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach, in ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 17, No. 3, Association for Computing Machinery, p. 26, May. 2021, ISSN: 1550-4832, 10.1145/3431389
Saxena, V., Reddy, A., Jonathan, N., Gustafson, J. L., Sangeeth, N., Leupers, R. and Merchant, F.: Brightening the Optical Flow through Posit Arithmetic, in International Symposium on Quality Electronic Design (ISQED), Apr. 2021, 10.1109/ISQED51717.2021.9424360 ©2021 IEEE
Alouani, I., BEN KHALIFA, A., Merchant, F. and Leupers, R.: An Investigation on Inherent Robustness of Posit Data Representation, in Proceedings of the International Conference on VLSI Design (VLSID), pp. 276-281, Feb. 2021, 10.1109/VLSID51830.2021.00052 ©2021 IEEE
Rai, S., Garg, S., Pilato, C., Herdt, V., Moussavi, E., Šišejković, D., Karri, R., Drechsler, R., Merchant, F. and Kumar, A.: Vertical IP Protection of the Next-Generation Devices: Quo Vadis?, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, 10.23919/DATE51398.2021.9474132

Alumni Postdoctoral Researcher: Haris Kremo