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  5. Farhad Merchant

Farhad Merchant

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Farhad Merchant, Ph. D.

Postdoctoral researcher

Room: 502
+49 241 80-27630
+49 241 80-28306
farhad.merchant(at)ice.rwth-aachen.de
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Biography

Farhad Merchant received his Ph.D. from the Indian Institute of Science, Bangalore (India) in 2016. His Ph.D. thesis title was "Algorithm-Architecture Co-design for Dense Linear Algebra Computations." He worked as a postdoctoral research fellow at Nanyang Technological University (NTU), Singapore from March 2016 to December 2016. In December 2016, he moved to Corporate Research in Robert Bosch in Bangalore as a Researcher where he worked on numerical methods for ordinary differential equations. He joined Institute for Communication Technologies and Embedded Systems, RWTH Aachen University in December 2017 as a postdoctoral research fellow in the Chair for Software for Systems on Silicon. 

Research Interests

  • Hardware Security
  • Hardware Assisted Security
  • Computer Architecture
  • Performance Modeling
  • Computer Arithmetic

Publications

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 24th IEEE European Test Symposium (ETS'19), May. 2019, accepted for publication ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2019


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: Applying Modified Householder Transform to Kalman Filter, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019, accepted for publication


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-design, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019, accepted for publication


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design, in Applied Reconfigurable Computing, May. 2018, 10.1007/978-3-319-78890-6


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization, in IEEE Transactions on Parallel and Distributed Systems, IEEE, Mar. 2018, 10.1109/TPDS.2018.2803820 ©2018 IEEE


Chaurasiya, R., John, G., Shrestha, R., Jonathan, N., Sangeeth, N., Kaustav, N., Merchant, F. and Leupers, R.: Parameterized Posit Arithmetic Hardware Generator, in Proceedings of the International Conference on Computer Design (ICCD), p. 8, 2018, accepted for publication ©2018 IEEE


Merchant, F., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design, in Parallel Processing Letters, Vol. 27, No. 03n04, World Scientific, pp. 1--17, Dec. 2017, 10.1142/S0129626417500062


Bhattacharjee, D., Merchant, F. and Chattopadhyay, A.: Enabling in-memory computation of binary {BLAS} using ReRAM crossbar arrays, in VLSI-SoC, Sep. 2016, ISBN: 978-1-50903-561-8, 10.1109/VLSI-SoC.2016.7753568 ©2016 IEEE


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation, in VLSI Design, pp. 98--103, 2016, ISBN: 978-1-46738-700-2, 10.1109/VLSID.2016.109 ©2016 IEEE


Merchant, F., Nimash, C., Nandy, S. K. and Narayan, R.: Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic, in VLSI Design, pp. 415--420, 2016, ISBN: 978-1-46738-700-2, 10.1109/VLSID.2016.113 ©2016 IEEE


Merchant, F., Maity, A., Mahadurkar,, M., Vatwani, K., Munje, I., Krishna C, M., Sivanandan, N., Gopalan, N., Raha, S., Nandy, S. K. and Narayan, R.: Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations, in VLSI Design, pp. 153--158, 2015, ISBN: 978-1-47996-658-5, 10.1109/VLSID.2015.31 ©2015 IEEE


Rákossy, Z. E., Merchant, F., Acosta Aponte, A., Nandy, S. K. and Chattopadhyay, A.: Scalable and Energy-Efficient Reconfigurable Accelerator for Column-Wise Givens Rotation, in 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)(Playa-del-Carmen, Mexico), IEEE, Oct. 2014, 10.1109/VLSI-SoC.2014.7004166 ©2014 IEEE


Rákossy, Z. E., Merchant, F., Acosta Aponte, A., Nandy, S. K. and Chattopadhyay, A.: Efficient and Scalable CGRA-based Implementation of Column-wise Givens Rotation, in 25th IEEE International Conference on Application-specific Systems, Architectures and Processors(Zuerich, Switzerland), Jun. 2014, 10.1109/ASAP.2014.6868659 ©2014 IEEE


Merchant, F., Chattopadhyay, A., Garga, G., Nandy, S. K. and Narajan, R.: Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR) , in 27th International Conference on VLSI Design, IIT Bombay, Mumbai India January 7-9, pp. 258 - 263 , 2014, ISSN: 1063-9667, 10.1109/VLSID.2014.51 ©2014 IEEE


Das, S., Madhu, K., Krishna C, M., Sivanandan, N., Merchant, F., Biswas, I., Pulli, A., Nandy, S. K. and Narayan, R.: A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths., in Journal of Systems Architecture - Embedded Systems Design, Vol. 60, No. 7, pp. 592--614, 2014, 10.1016/j.sysarc.2014.06.002


Mahadurkar,, M., Merchant, F., Maity, A., Vatwani, K., Munje, I., Gopalan, N., Nandy, S. K. and Narayan, R.: Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs, in SAMOS 2014, pp. 225--232, 2014, 10.1109/SAMOS.2014.6893215 ©2014 IEEE