Farhad Merchant

Publications from Jun/ 2022 to 2020

Moussavi, E., Šišejković, D., Brings, F., Kizatov, D., Singh, A., Xuan , T. V., Ingebrandt, S., Leupers, R., Pachauri, V. and Merchant, F.: pHGen: A pH-Based Key Generation Mechanism Using ISFETs, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Jun. 2022, accepted for publication ©2022 IEEE

Gansen, M., Lou, J., Freye, F., Gemmeke, T. , Merchant, F., Zeyer, A., Zeineldeen, M., Schlüter, R. and Fan, X.: Discrete Steps towards Approximate Computing, in ISQED , Apr. 2022, accepted for publication ©2022 IEEE

Galicia, M., Merchant, F. and Leupers, R.: A Parallel SystemC Virtual Platform for Neuromorphic Architectures, in International Symposium on Quality Electronic Design (ISQED) 2022, Apr. 2022

Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.: QFlow: Quantifying Data Leakage for RTL IP, in IEEE Council on Electronic Design Automation, Apr. 2022

Galicia, M., Menzel, S., Merchant, F., Müller, M., Chen, H.-Y. , Zhao, Q.-T. , Cüppers, F. , Jalil, A. R. , Shu, Q. , Schüffelgen, P., Mussler, G., Funck, C. , Lanius, C. , Wiefels, S. , von Witzleben, M. , Bengel, C. , Kopperberg, N. , Ziegler, T. , Walied, R. , Krüger, A. , Pöhls, L. , Dittmann, R. , Hoffmann-Eifert, S. , Rana, V., Grützmacher, D. , Wuttig, M. , Wouters, D. , Vescan, A. , Gemmeke, T. , Knoch, J. , Lemme, M. , Leupers, R. and Waser, R.: NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, accepted for publication ©2022 IEEE

Staudigl, F., Al Indari, H., Schön, D., Šišejković, D., Merchant, F., Joseph, J. M., Rana, V., Menzel, S. and Leupers, R.: NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2022, accepted for publication

Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.: QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog, in Proceedings of the International Conference on Computer Design (ICCD) , pp. 603-607, Oct. 2021, 10.1109/ICCD53106.2021.00097 ©2021 IEEE

Staudigl, F., Merchant, F. and Leupers, R.: A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators and Security, in IEEE Design & Test, Sep. 2021, 10.1109/MDAT.2021.3102013 ©2021 IEEE

Šišejković, D., Merchant, F., Reimann, L. M. and Leupers, R.: Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Jul. 2021, ISSN: 1937-4151, 10.1109/TCAD.2021.3100275 ©2021 IEEE

Šišejković, D., Merchant, F., Reimann, L. M., Srivastava, H., Hallawa, A. and Leupers, R.: Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach, in ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 17, No. 3, Association for Computing Machinery, p. 26, May. 2021, ISSN: 1550-4832, 10.1145/3431389

Saxena, V., Reddy, A., Jonathan, N., Gustafson, J. L., Sangeeth, N., Leupers, R. and Merchant, F.: Brightening the Optical Flow through Posit Arithmetic, in International Symposium on Quality Electronic Design (ISQED), Apr. 2021, 10.1109/ISQED51717.2021.9424360 ©2021 IEEE

Alouani, I., BEN KHALIFA, A., Merchant, F. and Leupers, R.: An Investigation on Inherent Robustness of Posit Data Representation, in Proceedings of the International Conference on VLSI Design (VLSID), pp. 276-281, Feb. 2021, 10.1109/VLSID51830.2021.00052 ©2021 IEEE

Rai, S., Garg, S., Pilato, C., Herdt, V., Moussavi, E., Šišejković, D., Karri, R., Drechsler, R., Merchant, F. and Kumar, A.: Vertical IP Protection of the Next-Generation Devices: Quo Vadis?, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, 10.23919/DATE51398.2021.9474132

Polian, I., Altmann, F., Arul, T., Boit, C., Brederlaw, R., Davi, L., Drechsler, R., Du, N., Eisenbarth, T., Gü­ney­su, T., Hermann, S., Hiller, M., Leupers, R., Merchant, F., Mussenbrock, T., Katzenbeisser, S., Kumar, A., Kunz, W., Mikolajick, T., Pachauri, V., Seifert, J.-P., Torres, F. S. and Trommer, J.: Nano Security: From Nano-Electronics to Secure Systems, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, 10.23919/DATE51398.2021.9474187

Merchant, F., Šišejković, D., Reimann, L. M., Yasotharan, K., Grass, T. and Leupers, R.: ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework, in Proceedings of the International Conference on VLSI Design (VLSID), 2021, 10.1109/VLSID51830.2021.00051 ©2021 IEEE

Šišejković, D., Reimann, L. M., Moussavi, E., Merchant, F. and Leupers, R.: Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities, in IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), 2021, 10.1109/VLSI-SoC53125.2021.9606979 ©2021 IEEE

Nambi, S., Ullah, S., Siva Satyendra, S., Lohana, A., Merchant, F. and Kumar, A.: ExPAN(N)D: Exploring Posits for EfficientArtificial Neural Network Design inFPGA-based Systems, in IEEE Access, Vol. 9, 2021, 10.1109/ACCESS.2021.3098730 ©2021 IEEE

Guntoro, A., De La Parra, C., Merchant, F., De Dinechin, F., Gustafson, J. L., Langhammer, M., Leupers, R. and Sangeeth, N.: Next Generation Arithmetic for Edge Computing, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), pp. 1357-1365, 2020, 10.23919/DATE48585.2020.9116196 ©2020 IEEE

Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R. and Kegreiß, S.: Scaling Logic Locking Schemes to Multi-Module Hardware Designs, in Architecture of Computing Systems (ARCS 2020), Springer International Publishing, pp. 138--152, 2020, 10.1007/978-3-030-52794-5_11 ©2020 IEEE

VREČA, J. , Sturm, K. J. X., GUNGL, E., Merchant, F., BIENTINESI, P., Leupers, R. and Brezočnik, Z.: Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit, in IEEE Access, 2020, 10.1109/ACCESS.2020.3022824} ©2020 IEEE

>>