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Melvin Galicia Cota, Ph. D.

Postdoctoral Researcher

Room: 508
+49 241 80-27988
+49 241 80-28306
melvin.galicia(at)ice.rwth-aachen.de
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Research Interests

Multicore microprocessor computer architectures
Modelling and simulation of microelectronic systems
Software development for embedded systems
Neuromorphic computing systems
Number theory, prime numbers and integer factorization

Biography

Melvin Galicia received his Ph.D. from Lodz University of Technology, Poland, in 2016. His dissertation's title was "Modelling of multicore processors for the investigation of temperature reduction techniques". He obtained his M.Sc. in electrical power engineering from the National Sun Yat-sen University of Taiwan in 2011. On both occasions he was a scholarship holder from E.U. Erasmus Mundus program and the TaiwanICDF program respectively. His B.Sc. degree in electronics was obtained from the University of San Carlos of Guatemala in 2008. Dr. Galicia has sound experience in the telecommunications industry. He worked as Senior Software engineer at the R&D department of Motorola Solutions developing 4G/LTE core systems for public safety applications. He also worked for Huawei Technologies as an information and communications technology (ICT) service solution manager. Moreover, he worked for Telefónica S.A. telecommunications provider as core and radio network engineer. Dr. Galicia joined the Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, in May 2020 as a postdoctoral research fellow in the Chair for Software for Systems on Silicon.

Publications

Happek, L., Huang, J.-T., Garcia Gener, A., Leupers, R. and Galicia, M.: Spiking Neural Networks for Signal Classification with Digital and Analog Neuromorphic Systems: A Comparative Study, in The International Joint Conference on Neural Networks (IJCNN) , Jul. 2024, accepted for publication ©2024 IEEE
Galicia, M., Osman, I., Owusu-Afriyie, C. and Leupers, R.: "S3cure": Scramble, Shuffle and Shambles - Secure Deployment of Weight Matrices in Memristor Crossbar Arrays, in Association for Computing Machinery, ACM, ICONS '23: Proceedings of the 2023 International Conference on Neuromorphic Systems, Aug. 2023, 10.1145/3589737.3605964
Galicia, M., Happek, L., Balzer, M. and Leupers, R.: Frequency and noise characterization for baseband signal processing on neuromorphic circuits, in 21st IEEE Interregional NEWCAS Conference (NEWCAS), Jun. 2023, 10.1109/NEWCAS57931.2023.10198095 ©2023 IEEE
Galicia, M., Merchant, F. and Leupers, R.: A Parallel SystemC Virtual Platform for Neuromorphic Architectures, in International Symposium on Quality Electronic Design (ISQED) 2022, Apr. 2022, 10.1109/ISQED54688.2022.9806235 ©2022 IEEE
Galicia, M., Menzel, S., Merchant, F., Müller, M., Chen, H.-Y. , Zhao, Q.-T. , Cüppers, F. , Jalil, A. R. , Shu, Q. , Schüffelgen, P., Mussler, G., Funck, C. , Lanius, C. , Wiefels, S. , von Witzleben, M. , Bengel, C. , Kopperberg, N. , Ziegler, T. , Walied, R. , Krüger, A. , Pöhls, L. , Dittmann, R. , Hoffmann-Eifert, S. , Rana, V., Grützmacher, D. , Wuttig, M. , Wouters, D. , Vescan, A. , Gemmeke, T. , Knoch, J. , Lemme, M. , Leupers, R. and Waser, R.: NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, 10.23919/DATE54114.2022.9774755 ©2022 IEEE
Galicia, M., BanaGozar, A., Sturm, K. J. X., Staudigl, F., Stuijk, S., Corporaal, H. and Leupers, R.: NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators, in International Conference on Communications and Technology, IEEE SOCC, 2021, 10.1109/SOCC52499.2021.9739585 ©2021 IEEE
Raszkowski, T., Zubert, M., Zajac, P., Nowak, P., Janicki, M., Samson, A., Galicia, M. and Napieralski, A.: DPL based electro-thermal modelling of Fin-FET transistors, in 2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), pp. 1093-1098, May. 2016, ISSN: 1087-9870, 10.1109/ITHERM.2016.7517669
Zajac, P., Galicia, M., Maj, C. and Napieralski, A.: Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors, in Microelectronics Journal, Vol. 52, pp. 40-48, 2016, ISSN: 0026-2692, 10.1016/j.mejo.2016.02.013
Zajac, P., Maj, C., Galicia, M. and Napieralski, A.: Coupled thermo-fluidic simulation for design space exploration of microchannels in liquid-cooled 3D ICs, in 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, pp. 257-261, 2016, 10.1109/MIXDES.2016.7529743
Zajac, P., Galicia, M., Maj, C. and Napieralski, A.: Investigation of localized thermal vias for temperature reduction in 3D multicore processors, in 2015 22nd International Conference Mixed Design of Integrated Circuits Systems (MIXDES), pp. 426-430, 2015, 10.1109/MIXDES.2015.7208556
Galicia, M., Zajac, P., Maj, C. and Napieralski, A.: Characterization of thermal vias for 3D ICs using FEM analysis, in 2015 21st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), pp. 1-4, 2015, 10.1109/THERMINIC.2015.7389616
Zajac, P., Maj, C., Galicia, M. and Napieralski, A.: Thermal Modelling of Modern Processors Using FEM and Compact Model, in International Journal of Microelectronics and Computer Science, Vol. 6, No. 3, pp. 110-116, 2015, ISSN: 2080-8755
Zajac, P., Galicia, M., Maj, C. and Napierlski, A.: Optimizing temperature distribution in modern processors through efficient floorplanning, in 20th International Workshop on Thermal Investigations of ICs and Systems, pp. 1-6, 2014, 10.1109/THERMINIC.2014.6972487
Galicia, M., Zajac, P., Maj, C., Szermer, M. and Napieralski, A.: Modelling modern processors using FEM and compact model — A comparative study, in 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), pp. 293-297, 2014, 10.1109/MIXDES.2014.6872204
Liu, C., Hung, K., Galicia, M. and Lin, S.: Systematic Integration Guidance for Alleviating Substation Congestion of Steel Mill Power Systems by Distributed Generation Units, in IEEE Transactions on Industry Applications, Vol. 50, No. 5, pp. 3113-3119, 2014, ISSN: 1939-9367, 10.1109/TIA.2014.2308361

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