HiPEAC CSW Spring 2022 – Special session on EDIHs


HiPEAC (research network on High Performance Embedded Architecture and Compilation) are organizing…

Lukas Jünger wins HiPEAC Technology Transfer Award 2021


2021 marks the seventh edition of the HiPEAC Tech Transfer Awards. This year, Lukas Jünger received…

Prof. Gačanin: Invited talk at Thinknet 6G Summit


6G perspective in 6GEM Research Hub

Prof. Gačanin is Keynote Speaker at IEEE Vehicular Technology Conference (VTC) 2021



More news

Latest Publications

Galicia Cota, M., Merchant, F. and Leupers, R.: A Parallel SystemC Virtual Platform for Neuromorphic Architectures, in ISQED, Apr. 2022, accepted for publication ©2022 IEEE

Galicia Cota, M., Menzel, S., Merchant, F., Müller, M., Chen, H.-Y. , Zhao, Q.-T. , Cüppers, F. , Jalil, A. R. , Shu, Q. , Schüffelgen, P., Mussler, G., Funck, C. , Lanius, C. , Wiefels, S. , von Witzleben, M. , Bengel, C. , Kopperberg, N. , Ziegler, T. , Walied, R. , Krüger, A. , Pöhls, L. , Dittmann, R. , Hoffmann-Eifert, S. , Rana, V., Grützmacher, D. , Wuttig, M. , Wouters, D. , Vescan, A. , Gemmeke, T. , Knoch, J. , Lemme, M. , Leupers, R. and Waser, R.: NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, accepted for publication ©2022 IEEE

Staudigl, F., Al Indari, H., Schön, D., Šišejković, D., Merchant, F., Joseph, J. M., Rana, V., Menzel, S. and Leupers, R.: NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2022, accepted for publication

The Institute for Communication Technologies and Embedded Systems (ICE) is jointly directed by Prof. Rainer Leupers (Chair for Software for Systems on Silicon, SSS) and Prof. Haris Gačanin (Chair for Distributed Signal Processing, DSP), who collaborate closely in research and complement each other with their expertise.

Key research areas at ICE:

  • Wireless signal processing and networking for wireless communication systems: from algorithm to implementation
  • Intelligent systems and short-range communication systems (e.g. AI-based RRM, D2D, Cyber Physical Systems, M2M, Wireless 2.0)
  • Design of sensors with convergence of signal processing and machine learning methodologies
  • Efficient hardware accelerators and processor architectures for embedded applications, in particular multiprocessor systems-on-chip (MPSoC)
  • Electronic system-level (ESL) design tools for application-specific HW/SW systems
  • Software development tools (e.g. compilers and fast simulators) for heterogeneous multicore architectures
  • Hardware security


Institute for Communication Technologies and Embedded Systems

Chair for Software for Systems on Silicon
Univ.-Prof. Dr. rer. nat. Rainer Leupers
+49 241 80-28301

Chair for Distributed Signal Processing
Univ.-Prof. Dr. Haris Gačanin
+49 241 80-27880

Kopernikusstraße 16
52074 Aachen

How to find us

Hardware Hacking Space: "Machine Learning vs. Hardware Integrity Protection: Who will prevail?"

NOCS 2021 - NEWROMAP: Mapping CNNs to Self-contained Data-flow Accelerators for Edge-AI

ACM Nanocom 2021 - Technology-aware Router Architectures for On-Chip-Networks

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog

NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators