Prof. Gačanin: Invited talk at Thinknet 6G Summit


6G perspective in 6GEM Research Hub

Prof. Gačanin is Keynote Speaker at IEEE Vehicular Technology Conference (VTC) 2021



Dominik Šišejković wins best PhD award at VLSI-SoC'21


The doctoral work of Dominik Šišejković, titled "Trustworthy Hardware Design with Logic Locking",…

ICE spin-off Silexica acquired by Xilinx


Following comprehensive research activities within the UMIC Excellence Cluster, Silexica has been…

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Latest Publications

Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.: QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog, in Proceedings of the International Conference on Computer Design (ICCD) , Oct. 2021, accepted for publication ©2021 IEEE

Joseph, J. M., Baloglu, M. S. , Pan, Y., Leupers, R. and Bamberg, L.: NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI, in NOCS '21: Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip, p. 15–20, Oct. 2021, 10.1145/3479876.3481591

Staudigl, F., Merchant, F. and Leupers, R.: A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators and Security, in IEEE Design & Test, Sep. 2021, accepted for publication ©2021 IEEE

The Institute for Communication Technologies and Embedded Systems (ICE) is jointly directed by Prof. Rainer Leupers (Chair for Software for Systems on Silicon, SSS) and Prof. Haris Gačanin (Chair for Distributed Signal Processing, DSP), who collaborate closely in research and complement each other with their expertise.

Key research areas at ICE:

  • Wireless signal processing and networking for wireless communication systems: from algorithm to implementation
  • Intelligent systems and short-range communication systems (e.g. AI-based RRM, D2D, Cyber Physical Systems, M2M, Wireless 2.0)
  • Design of sensors with convergence of signal processing and machine learning methodologies
  • Efficient hardware accelerators and processor architectures for embedded applications, in particular multiprocessor systems-on-chip (MPSoC)
  • Electronic system-level (ESL) design tools for application-specific HW/SW systems
  • Software development tools (e.g. compilers and fast simulators) for heterogeneous multicore architectures
  • Hardware security


Institute for Communication Technologies and Embedded Systems

Chair for Software for Systems on Silicon
Univ.-Prof. Dr. rer. nat. Rainer Leupers
+49 241 80-28301

Chair for Distributed Signal Processing
Univ.-Prof. Dr. Haris Gačanin
+49 241 80-27880

Kopernikusstraße 16
52074 Aachen

How to find us

NOCS 2021 - NEWROMAP: Mapping CNNs to Self-contained Data-flow Accelerators for Edge-AI

ACM Nanocom 2021 - Technology-aware Router Architectures for On-Chip-Networks

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog

NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators

Bridging the Frequency Gap in Heterogeneous 3D SoCs with Technology-Specific NoCs