News

Final TETRAMAX review meeting

Feb 18 2022

On 02/18/2022  the final TETRAMAX review meeting was successfully finished

HiPEAC CSW Spring 2022 – Special session on EDIHs

Jan 03 2022

HiPEAC (research network on High Performance Embedded Architecture and Compilation) are organizing…

New TETRAMAX video

Jan 03 2022

A short TETRAMAX summary video clip was produced

Lukas Jünger wins HiPEAC Technology Transfer Award 2021

Dec 17 2021

2021 marks the seventh edition of the HiPEAC Tech Transfer Awards. This year, Lukas Jünger received…

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Latest Publications

Moussavi, E., Šišejković, D., Brings, F., Kizatov, D., Singh, A., Xuan , T. V., Ingebrandt, S., Leupers, R., Pachauri, V. and Merchant, F.: pHGen: A pH-Based Key Generation Mechanism Using ISFETs, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Jun. 2022, accepted for publication ©2022 IEEE


Gansen, M., Lou, J., Freye, F., Gemmeke, T. , Merchant, F., Zeyer, A., Zeineldeen, M., Schlüter, R. and Fan, X.: Discrete Steps towards Approximate Computing, in ISQED , Apr. 2022, accepted for publication ©2022 IEEE


Cheng, C., Guo, L., Wu, T., Sun, J., Gui, G., Abedisi, B., Gacanin, H. and Sari, H.: Machine-Learning-Aided Trajectory Prediction and Conflict Detection for Internet of Aerial Vehicles, in IEEE Internet of Things Journal, Vol. 9, No. 8, pp. 5882-5894, Apr. 2022, ISSN: 2327-4662, 10.1109/JIOT.2021.3060904 ©2022 IEEE


The Institute for Communication Technologies and Embedded Systems (ICE) is jointly directed by Prof. Rainer Leupers (Chair for Software for Systems on Silicon, SSS) and Prof. Haris Gačanin (Chair for Distributed Signal Processing, DSP), who collaborate closely in research and complement each other with their expertise.

Key research areas at ICE:

  • Wireless signal processing and networking for wireless communication systems: from algorithm to implementation
  • Intelligent systems and short-range communication systems (e.g. AI-based RRM, D2D, Cyber Physical Systems, M2M, Wireless 2.0)
  • Design of sensors with convergence of signal processing and machine learning methodologies
  • Efficient hardware accelerators and processor architectures for embedded applications, in particular multiprocessor systems-on-chip (MPSoC)
  • Electronic system-level (ESL) design tools for application-specific HW/SW systems
  • Software development tools (e.g. compilers and fast simulators) for heterogeneous multicore architectures
  • Hardware security

Contact

Institute for Communication Technologies and Embedded Systems

Chair for Software for Systems on Silicon
Univ.-Prof. Dr. rer. nat. Rainer Leupers
+49 241 80-28301

Chair for Distributed Signal Processing
Univ.-Prof. Dr. Haris Gačanin
+49 241 80-27880

Kopernikusstraße 16
52074 Aachen
Germany
sekretariat(at)ice.rwth-aachen.de

How to find us


CAD for Assurance: QFlow: Quantifying Data Leakage and QIF-RTL: A New Secure Description Language

A Parallel SystemC Virtual Platform for Neuromorphic Architectures

Hardware Hacking Space: "Machine Learning vs. Hardware Integrity Protection: Who will prevail?"

NOCS 2021 - NEWROMAP: Mapping CNNs to Self-contained Data-flow Accelerators for Edge-AI

ACM Nanocom 2021 - Technology-aware Router Architectures for On-Chip-Networks