The Institute for Communication Technologies and Embedded Systems (ICE) is jointly directed by Prof. Gerd Ascheid (Chair for Integrated Signal Processing Systems, ISS) and Prof. Rainer Leupers (Chair for Software for Systems on Silicon, SSS), who collaborate closely in research and complement each other with their expertise.

Key research areas at ICE:

  • Digital receivers for wireless communication systems: from algorithm to implementation
  • M2M communication systems (e.g. in Cyber Physical Systems)
  • Sensor signal processing and machine learning
  • Hardware and chip architectures for embedded systems and IoT devices, in particular multiprocessor systems-on-chip (MPSoC)
  • Electronic system-level (ESL) design tools for complex integrated circuits and systems
  • Software development tools for heterogeneous multicore architectures
  • Hardware security

Contact

Institute for Communication Technologies and Embedded Systems

Chair for Integrated Signal Processing Systems
Univ.-Prof. Dr.-Ing. Gerd Ascheid,
+49 241 80-27880

Chair for Software for Systems on Silicon
Univ.-Prof. Dr. rer. nat. Rainer Leupers,
+49 241 80-28301

Kopernikusstraße 16
52074 Aachen
Germany
sekretariat(at)ice.rwth-aachen.de

How to find us

News

ICE organizes a hardware security workshop at HiPEAC 2019

Oct252018

Along with Prof. Avi Mendelson from Technion, ICE's Prof. Rainer Leupers, Farhad Merchant and Do…

Publication of Third Edition of Handbook of Signal Processing Systems

Oct252018

Bhattacharyya, S.S.; Deprettere, E.F.; Leupers, R.; Takala, J. (Eds.), 3rd Edition., 2018-09-20,…

Synopsys ASIP University Day 2018 - Europe

Sep262018

ASIP University Day 2018 took place at ICE on Wednesday, September 26th, 2018

More news

Latest Publications

Dartmann, G. (Ed.), Song, H. (Ed.) and Schmeink, A. (Ed.): Big Data Analytics for Cyber-Physical Systems, Elsevier, Jul. 2019, accepted for publication, ISBN: 978-0-12816-637-6


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 24th IEEE European Test Symposium (ETS'19), May. 2019, accepted for publication ©2019 IEEE


Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Feb. 2019, accepted for publication, 10.1109/LES.2019.2901224