Latest Publications
Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.:
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog,
in
Proceedings of the International Conference on Computer Design (ICCD)
,
Oct. 2021, accepted for publication ©2021 IEEE
Staudigl, F., Merchant, F. and Leupers, R.:
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators and Security,
in IEEE Design & Test,
Sep. 2021, accepted for publication ©2021 IEEE
Liang, Z. and Ascheid, G.:
Subcarrier Grouping with Linear Time-Domain Compensation for Low-Complexity Millimeter Wave OFDM Multiuser Systems,
in
Proceedings of IEEE Vehicular Technology Conference (VTC-Fall),
IEEE,
Sep. 2021, accepted for publication
The Institute for Communication Technologies and Embedded Systems (ICE) is jointly directed by Prof. Rainer Leupers (Chair for Software for Systems on Silicon, SSS) and Prof. Haris Gačanin (Chair for Distributed Signal Processing, DSP), who collaborate closely in research and complement each other with their expertise.
Key research areas at ICE:
- Wireless signal processing and networking for wireless communication systems: from algorithm to implementation
- Intelligent systems and short-range communication systems (e.g. AI-based RRM, D2D, Cyber Physical Systems, M2M, Wireless 2.0)
- Design of sensors with convergence of signal processing and machine learning methodologies
- Efficient hardware accelerators and processor architectures for embedded applications, in particular multiprocessor systems-on-chip (MPSoC)
- Electronic system-level (ESL) design tools for application-specific HW/SW systems
- Software development tools (e.g. compilers and fast simulators) for heterogeneous multicore architectures
- Hardware security
Contact
Institute for Communication Technologies and Embedded Systems
Chair for Software for Systems on Silicon | Chair for Distributed Signal Processing |
Kopernikusstraße 16
52074 Aachen
Germany
sekretariat(at)ice.rwth-aachen.de
NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators
ACM Nanocom 2021 - Technology-aware Router Architectures for On-Chip-Networks
Bridging the Frequency Gap in Heterogeneous 3D SoCs with Technology-Specific NoCs
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators