Institute for Communication Technologies and Embedded Systems


par-gem5: Parallelizing gem5 s Atomic Mode, in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6, 2023, 10.23919/DATE56975.2023.10137178
Zurstraßen, N., Cubero-Cascante, J., Joseph, J. M., Yichao, L., Xinghua, X. and Leupers, R.
A Parallel SystemC Virtual Platform for Neuromorphic Architectures, in International Symposium on Quality Electronic Design (ISQED) 2022, Apr. 2022, 10.1109/ISQED54688.2022.9806235 ©2022 IEEE
Galicia, M., Merchant, F. and Leupers, R.
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI, in NOCS '21: Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip, p. 15–20, Oct. 2021, 10.1145/3479876.3481591
Joseph, J. M., Baloglu, M. S. , Pan, Y., Leupers, R. and Bamberg, L.
Bridging the F requency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), 2021, 10.1145/3394885.3431421
Joseph, J. M., Bamberg, L., Geonhwa, J., Chien, R.-T., Leupers, R., García-Ortiz, A., Krishna, T. and Pionteck, T.
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators, in International Symposium on Quality Electronic Design (ISQED), 2021, 10.1109/ISQED51717.2021.9424349
Joseph, J. M., Samajdar, A., Zhu, L., Leupers, R., Lim, S.-K., Pionteck, T. and Krishna, T.