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Lennart Reimann, M.Sc.

Chief Engineer

Room: 504
+49 241 80-27628
+49 241 80-28306
Lennart.Reimann(at)ice.rwth-aachen.de
View LinkedIn Profile

Teaching

Student assistants:

Yu Duan
Yadu Variyar

Master students:

Karol Jaszczyk

Bachelor students:

Evgenii Rezunov

Projects

Tools Projects: Hardware Security: Secure Processor Design
Collaborative Projects: ZUSE-KI-AVF

Biography

Lennart Reimann received his Bachelor's and Master's degree in Electrical Engineering, Information Technology, and Computer Engineering from RWTH Aachen University in 2016 and 2019, respectively. During his Bachelor's degree, he started working as a student assistant at the Institute for Communication Technologies and Embedded Systems (ICE), which he continued through his Master's degree. His work at ICE was in the field of ASIP design for several applications, mainly in the field of Machine Learning. After his Master's, he started working toward his Ph.D. as a research assistant at ICE under the supervision of Prof. Leupers. His research interest includes Hardware Security, Secure ASIP design, Cryptographic accelerator design, etc.

Publications

Thieu, G. B., Gesper, S., Paya Vaya, G., Riggers, C., Renke, O., Fiedler, T., Marten, J., Stuckenberg, T., Blume, H., Weis, C., Steiner, L., Sudarshan, C., Wehn, N., Reimann, L. M., Leupers, R., Beyer, M., Köhler, D., Jauch, A., Bormann, J. M., Jaberansari, S., Berthold, T., Blawat, M., Kock, M., Schewior, G., Benndorf, J., Kautz, F., Bluethgen, H.-M. and Sauer, C.: ZuSE-KI-AVF: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2023, accepted for publication
Reimann, L. M., Erdonmez, S., Šišejković, D. and Leupers, R.: Quantitative Information Flow for Hardware: Advancing the Attack Landscape, in LASCAS 2023, Nov. 2022, accepted for publication, 10.48550/arXiv.2211.16891
Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.: QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog, in Proceedings of the International Conference on Computer Design (ICCD) , pp. 603-607, Oct. 2021, 10.1109/ICCD53106.2021.00097 ©2021 IEEE
Šišejković, D., Merchant, F., Reimann, L. M. and Leupers, R.: Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Jul. 2021, ISSN: 1937-4151, 10.1109/TCAD.2021.3100275 ©2021 IEEE
Šišejković, D., Merchant, F., Reimann, L. M., Srivastava, H., Hallawa, A. and Leupers, R.: Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach, in ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 17, No. 3, Association for Computing Machinery, p. 26, May. 2021, ISSN: 1550-4832, 10.1145/3431389
Merchant, F., Šišejković, D., Reimann, L. M., Yasotharan, K., Grass, T. and Leupers, R.: ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework, in Proceedings of the International Conference on VLSI Design (VLSID), 2021, 10.1109/VLSID51830.2021.00051 ©2021 IEEE
Šišejković, D., Reimann, L. M., Moussavi, E., Merchant, F. and Leupers, R.: Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities, in IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), 2021, 10.1109/VLSI-SoC53125.2021.9606979 ©2021 IEEE
Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R. and Kegreiß, S.: Scaling Logic Locking Schemes to Multi-Module Hardware Designs, in Architecture of Computing Systems (ARCS 2020), Springer International Publishing, pp. 138--152, 2020, 10.1007/978-3-030-52794-5_11 ©2020 IEEE
Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R., Giacometti, M. and Kegreiß, S.: A Secure Hardware-Software Solution Based on RISC-V, Logic Locking and Microkernel, in Proceedings of the 23nd International Workshop on Software and Compilers for Embedded Systems (SCOPES), p. 62–65, Association for Computing Machinery, 2020, 10.1145/3378678.3391886 ©2020 IEEE

Videos

QFlow: Quantifying Data Leakage for RTL IP

ICCD 2021 - QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog