Institute for Communication Technologies and Embedded Systems

Project: Embedded Processor Design and Optimization


Application-Specific Instruction Set Architectures (ASIPs) are finding widespread use in virtually all embedded ICT domains, including wireless communication, smartphones, automotive, computer vision, and many others. Evolution in technology has enabled system architects to devise increasingly complex devices, composed of several heterogeneous elements such as hardware accelerators, general purpose controllers and digital signal processing controllers. ASIPs are optimized for an application of a specific domain, while retaining most of the flexibility of General Purpose Processors (GPPs).

Especially in the field of low-energy end devices, such as smartphones, ASIPs are used to allow computations with a reduced energy consumption and increased performance compared to running the same application on GPPs. In the world of Internet of Things (IoT) the amount of end devices in use increases daily. A major concern is the factor of security, so that most of the device’s communication is encrypted and secured using the TLS protocol. The cryptographic algorithms used in this protocol, such as AES and SHA, are computationally extensive. That’s why many manufacturers use dedicated hardware to reduce energy consumption and increase the performance.

This lab course provides hands-on experience in ASIP-Design using Architecture Description Languages like nML to modify a RISC-V processor’s instruction set and architecture to accelerate cryptographic applications. Designing and simulating will be done using Synopsys ASIP-Designer.

Related projects:

Lecturer:  Rainer Leupers

Supervisors:  Lennart Reimann, Lorenzo Pfeifer

Project RWTH Online

Course programme: Master

Credits: 4

Course language: German, English

Course language: English


  1. Register via RWTH online
  2. Attend the introduction event (see below)

Room: ICT cubes 431

Introduction: 17.04.2024 17:30