Institute for Communication Technologies and Embedded Systems

Seminar: Embedded System Design - B.Sc.

The Embedded Systems Seminar will cover the topic: RISC-V.

 

RISC-V is an open source instruction set architecture (ISA) that has gained significant attention in recent years. Unlike proprietary ISAs, RISC-V can be freely used, modified and distributed, making it an attractive alternative to traditional architectures. The RISC-V ISA was originally developed at the University of California, Berkeley, with the goal of providing a simple, extensible, and standardized ISA that could be used in computing devices such as embedded systems.

The open source nature, modularity, and simplicity of RISC-V make it a promising alternative to proprietary ISAs for a wide range of applications. As the RISC-V ecosystem continues to grow and mature, it is likely to become an even more attractive option for developers and system designers.

 

Lecturer:  Prof. Rainer Leupers

Seminar RWTHOnline

Room

ICT cubes, Seminar room 431

Course language: English

 

Registration:
After applying via RWTH online: To register to this course, please attend the introduction event on Thursday 18.04.2024, 17:30 hrs. Location: Room 431, 4th floor, Kopernikusstra├če 16, 52074 Aachen (ICT cubes). At this event, you will receive the information on how to register for the course. Only after the registration, if accepted, you will be placed in the course.

For more information, please contact: galicia(at)ice.rwth-aachen.de