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CLARINET: A Quire-Enabled RISC-V-Based Framework for Posit Arithmetic Empiricism

Authors:
Sharma, N. N. ,  Jain , R. ,  Pokkuluri, M. M. ,  Patkar, S. ,  Leupers, R. ,  Nikhil, R. S. ,  Merchant, F.
Journal:
Journal of Systems Architecture (Elsevier)
Status:
accepted for publication
Date:
2023
Language:
English
Abstract:
Many applications require high-precision arithmetic. IEEE 754-2019 compliant (floating-point) arithmetic is the de facto standard for performing these computations. Recently, posit-arithmetic has been proposed as a drop-in replacement for floating-point arithmetic. The posit data representation and arithmetic claim several advantages over the floating-point format and arithmetic, including higher dynamic range, better accuracy, and superior performance-area trade-offs. However, very few accessible and holistic frameworks facilitate the validation of these claims of posit-arithmetic, especially with long accumulations (quire).

We present a consolidated general-purpose processor-based framework to support posit-arithmetic empiricism. Users can seamlessly experiment using posit and floating-point arithmetic in their applications since the framework is designed for the two number systems to coexist. Melodica is a posit-arithmetic core that implements parametric fused operations on the quire data type. Clarinet is a Melodica-enabled processor based on the RISC-V ISA. To the best of our knowledge, this is the first-ever integration of the quire in a RISC-V core. We report results from application studies on Clarinet and benchmark common linear algebra and computer vision kernels. We synthesize Clarinet on a Xilinx FPGA and present utilization and timing data. Clarinet and Melodica remain actively under development and are available as open-source.
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