Institute for Communication Technologies and Embedded Systems

Entropy-Based Analysis of Benchmarks for Instruction Set Simulators

Authors:
Bosbach, N.Jünger, L.Pelke, R.Zurstraßen, N.Leupers, R.
Book Title:
RAPIDO2023: Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems
Publisher:
Association for Computing Machinery
Series:
RAPIDO2023
Pages:
p.p. 54-59
Address:
New York, NY, USA
Date:
Jan. 2023
Note:

Toulouse, France

ISBN:
979-8-40070-045-3
DOI:
10.1145/3579170.3579267
hsb:
RWTH-2023-03503
Language:
English
Abstract:
Instruction-Set Simulators (ISSs) are widely used to simulate the execution of programs for a target architecture on a host machine. They translate the instructions of the program that should be executed into instructions of the host Instruction-Set Architecture (ISA). The performance of ISSs strongly depends on the implementation and the instructions that should be executed. Therefore, benchmarks that are used to compare the performance of ISSs should contain a variety of instructions. Since many benchmarks are written in high-level programming languages, it is usually not clear to the user which instructions are underlying the benchmarks. In this work, we present a tool that can be used to analyze the variety of instructions used in a benchmark. In a multi-stage analysis, the properties of the benchmarks are collected. An entropy-based metric is used to measure the diversity of the instructions used by the benchmark. In a case study, we present results for the benchmarks Whetstone, Dhrystone, Coremark STREAM, and stdcbench. We show the diversity of those benchmarks for different compiler optimizations and indicate which benchmarks should be used to test the general performance of an ISS.
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