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Mapping of CNNs on multi-core RRAM-based CIM architectures

Authors:: Pelke, R. , Bosbach, N. , Cubero-Cascante, J. , Staudigl, F. , Leupers, R. , Joseph, J. M.
Book Title:: 2023 IFIP/IEEE 31th International Conference on Very Large Scale Integration (VLSI-SoC)
Date:: Oct. 2023
DOI:: 10.48550/arXiv.2309.03805
hsb:: RWTH-2023-12091
Language:: English
Abstract:: RRAM-based multi-core systems improve the energy efficiency and performance of CNNs. Thereby, the distributed parallel execution of convolutional layers causes critical data dependencies that limit the potential speedup. This paper presents synchronization techniques for parallel inference of convolutional layers on RRAM-based CIM architectures. We propose an architecture optimization that enables efficient data exchange and discuss the impact of different architecture setups on the performance. The corresponding compiler algorithms are optimized for high speedup and low memory consumption during CNN inference. We achieve more than 99% of the theoretical acceleration limit with a marginal data transmission overhead of less than 4% for state-of-the-art CNN benchmarks.
Download:: BibTeX