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Dr.-Ing. Jan Moritz Joseph

Senior Researcher

Room: 506
+49 241 80-28305
+49 241 80-28306
joseph(at)ice.rwth-aachen.de
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Research Interests

DNN-Accelerators
On-Chip Learning
Machine Learning
Simulation
Networks-on-Chip
3D Integration

Student assistants:

Maximilian Bartel

Bachelor students:

Roberto Laudani

Biography & CV

Dr. Joseph's CV

Dr. Joseph got his B.Sc. in medical engineering in 2011 and his M.Sc. in computer science in 2014 from the Universität zu Lübeck, Germany. From 2008 to 2014 he was a scholarship holder of the German Merit Foundation (Deutsche Studienstiftung e.V.). Dr. Joseph received his Ph.D. from Otto-von-Guericke Universität Magdeburg, Germany, in 2019. The title of his thesis was "Networks-on-Chip for heterogeneous 3D Systems-on-Chip". His Ph.D. was awarded the highest honors “summa cum laude”. In 2020, he received the award for the best PhD thesis from the Faculty of Electrical Engineering and Information Technology at Otto-von-Guericke Universität Magdeburg, Germany.

From 2019 to 2020 Dr. Joseph was a visiting researcher at Dr. Krishna’s Synergy Lab at Georgia Institute of Technology, Atlanta, GA. His stay was partially funded by a scholarship from the German Academic Exchange Service.

He joined Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, in June 2020 as a postdoctoral research fellow in the Chair for Software for Systems on Silicon.

Publications

Publications from 2023 to 2018

Zurstraßen, N., Jose, C.-C., Joseph, J. M., Leupers, R., Xinghua, X. and Yichao, L.: par-gem5: Parallelizing gem5 s Atomic Mode, in 2023 Design, Automation and Test in Europe Conference (DATE), 2023, accepted for publication
Staudigl, F., Al Indari, H., Schön, D., Šišejković, D., Merchant, F., Joseph, J. M., Rana, V., Menzel, S. and Leupers, R.: NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, 10.23919/DATE54114.2022.9774651 ©2022 IEEE
Bosbach, N., Jünger, L., Joseph, J. M. and Leupers, R.: NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool, in 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC) , IEEE, 2022, ISBN: 978-1-66549-006-1, ISSN: 2324-8440, 10.1109/VLSI-SoC54400.2022.9939578 ©2022 IEEE
Staudigl, F., Sturm, K. J. X., Bartel, M., Fetz, T., Šišejković, D., Joseph, J. M., Bolzani Pöhls, L. and Leupers, R.: X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation, in International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, accepted for publication ©2022 IEEE
Joseph, J. M., Baloglu, M. S. , Pan, Y., Leupers, R. and Bamberg, L.: NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI, in NOCS '21: Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip, p. 15–20, Oct. 2021, 10.1145/3479876.3481591
Joseph, J. M., Bamberg, L., Hajjar, I., Perjikolaei, B., García-Ortiz, A. and Pionteck, T.: Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs, in ACM Trans. Model. Comput. Simul., Vol. 32, No. 1, Association for Computing Machinery, New York, NY, USA, p. 21, Sep. 2021, ISSN: 1049-3301, 10.1145/3472754
Joseph, J. M., Bamberg, L., Geonhwa, J., Chien, R.-T., Leupers, R., García-Ortiz, A., Krishna, T. and Pionteck, T.: Bridging the F requency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), 2021, 10.1145/3394885.3431421
Joseph, J. M., Samajdar, A., Zhu, L., Leupers, R., Lim, S.-K., Pionteck, T. and Krishna, T.: Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators, in International Symposium on Quality Electronic Design (ISQED), 2021, 10.1109/ISQED51717.2021.9424349
Bamberg, L., Krishna, T. and Joseph, J. M.: Technology-Aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies, in Proceedings of the Eight Annual ACM International Conference on Nanoscale Computing and Communication, Association for Computing Machinery, New York, NY, USA, 2021, ISBN: 978-1-45038-710-1, 10.1145/3477206.3477457
Joseph, J. M., Ermel, D., Bamberg, L., García-Ortiz, A. and Pionteck, T.: Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing, in Technologies, Vol. 8, No. 10, MDPI, 2020, 10.3390/technologies8010010
Drewes, A., Joseph, J. M., Gurumurthy, B., Broneske, D., Saake, G. and Pionteck, T.: Optimising Operator Sets for Analytical Database Processing on FPGAs, in ARC, 2020, 10.1007/978-3-030-44534-8_3
Samajdar, A., Joseph, J. M., Zhu, Y., Whatmough, P., Mattina, M. and Krishna, T.: A systematic methodology for characterizing scalability of DNN accelerators using SCALE-sim, in ISPASS, 2020, 10.1109/ISPASS48437.2020.00016 ©2020 IEEE
Joseph, J. M., Ermel, D., Drewes, T., Bamberg, L., García-Ortiz, A. and Pionteck, T.: Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips, in 8th International Conference on Modern Circuits and Systems Technologies (MOCAST), pp. 1-4, 2019, 10.1109/MOCAST.2019.8742035 ©2019 IEEE
Joseph, J. M., Bamberg, L., Ermel, D., Perjikolaei, B., Drewes, A., García-Ortiz, A. and Pionteck, T.: NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures, in IEEE Access, Vol. 7, pp. 135145-135163, 2019, 10.1109/ACCESS.2019.2942129 ©2019 IEEE
Joseph, J. M., Ermel, D., Bamberg, L., Oritz, A. and Pionteck, T.: System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips, in 2019 IEEE 37th International Conference on Computer Design (ICCD), pp. 409-412, 2019, 10.1109/ICCD46524.2019.00064 ©2019 IEEE
Passaretti, D., Joseph, J. M. and Pionteck, T.: Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models, in International Conference on Field-Programmable Technology (ICFPT), pp. 279-282, 2019, 10.1109/ICFPT47387.2019.00047 ©2019 IEEE
Bamberg, L., Joseph, J. M., Pionteck, T. and García-Ortiz, A.: Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment, in Integration, Vol. 67, pp. 60-72, 2019, 10.1016/j.vlsi.2019.04.009
Joseph, J. M., Bamberg, L., Hajjar, I., Schmidt, R., Pionteck, T. and García-Ortiz, A.: Simulation environment for link energy estimation in networks-on-chip with virtual channels, in Integration, Vol. 68, pp. 147-156, 2019, 10.1016/j.vlsi.2019.05.005
Bamberg, L., Joseph, J. M., Schmidt, R., Pionteck, T. and García-Ortiz, A.: Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels, in 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 222-228, 2018, 10.1109/PATMOS.2018.8464171
Joseph, J. M., Bamberg, L., Krell, G., Hajjar, I., García-Ortiz, A. and Pionteck, T.: Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs, in 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-8, 2018, 10.1109/ReCoSoC.2018.8449387 ©2018 IEEE

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