Jan Moritz Joseph

Dr.-Ing. Jan Moritz Joseph

Postdoctoral researcher

Room: 508
+49 241 80-27874
+49 241 80-28306
joseph(at)ice.rwth-aachen.de

Biography

Dr. Joseph got his B.Sc. in medical engineering in 2011 and his M.Sc. in computer science in 2014 from the Universität zu Lübeck, Germany.  From 2008 to 2014 he was a scholarship holder of the German Merit Foundation (Deutsche Studienstiftung e.V.). Dr. Joseph received his Ph.D. from Otto-von-Guericke Universität Magdeburg, Germany, in 2019. The title of his thesis was "Networks-on-Chip for heterogeneous 3D Systems-on-Chip". His Ph.D. was awarded the highest honors “summa cum laude”. From 2019 to 2020 Dr. Joseph was a visiting researcher at Dr. Krishna’s Synergy Lab at Georgia Institute of Technology, Atlanta, GA. His stay was partially funded by a scholarship from the German Academic Exchange Service. He joined Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, in June 2020 as a postdoctoral research fellow in the Chair for Software for Systems on Silicon.

Research Interests

  • Simulation
  • Networks-on-Chip
  • 3D Integration

Publications

Publications from 2019 to 2015

Joseph, J. M., Ermel, D., Drewes, T., Bamberg, L., García-Oritz, A. and Pionteck, T.: Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips, in 8th International Conference on Modern Circuits and Systems Technologies (MOCAST), pp. 1-4, 2019, 10.1109/MOCAST.2019.8742035 ©2019 IEEE


Joseph, J. M., Bamberg, L., Ermel, D., Perjikolaei, B., Drewes, A., García-Ortiz, A. and Pionteck, T.: NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures, in IEEE Access, Vol. 7, pp. 135145-135163, 2019, 10.1109/ACCESS.2019.2942129 ©2019 IEEE


Joseph, J. M., Ermel, D., Bamberg, L., Oritz, A. and Pionteck, T.: System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips, in 2019 IEEE 37th International Conference on Computer Design (ICCD), pp. 409-412, 2019, 10.1109/ICCD46524.2019.00064 ©2019 IEEE


Passaretti, D., Joseph, J. M. and Pionteck, T.: Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models, in International Conference on Field-Programmable Technology (ICFPT), pp. 279-282, 2019, 10.1109/ICFPT47387.2019.00047 ©2019 IEEE


Bamberg, L., Joseph, J. M., Pionteck, T. and García-Ortiz, A.: Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment, in Integration, Vol. 67, pp. 60-72, 2019, 10.1016/j.vlsi.2019.04.009


Joseph, J. M., Bamberg, L., Hajjar, I., Schmidt, R., Pionteck, T. and García-Ortiz, A.: Simulation environment for link energy estimation in networks-on-chip with virtual channels, in Integration, Vol. 68, pp. 147-156, 2019, 10.1016/j.vlsi.2019.05.005


Bamberg, L., Joseph, J. M., Schmidt, R., Pionteck, T. and García-Ortiz, A.: Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels, in 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 222-228, 2018, 10.1109/PATMOS.2018.8464171


Joseph, J. M., Bamberg, L., Krell, G., Hajjar, I., García-Oritz, A. and Pionteck, T.: Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs, in 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-8, 2018, 10.1109/ReCoSoC.2018.8449387 ©2018 IEEE


Blochwitz, C., Wolff, J., Berekovic, M., Heinrich, D., Groppe, S., Joseph, J. M. and Pionteck, T.: Hardware-Accelerated Index Construction for Semantic Web, in International Conference on Field-Programmable Technology (FPT), pp. 278-281, 2018, 10.1109/FPT.2018.00053 ©2018 IEEE


Drewes, T., Joseph, J. M., Gurumurthy, B., Broneske, D., Saake, G. and Pionteck, T.: Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs, in International Conference on Field-Programmable Technology (FPT), pp. 266-269, 2018, 10.1109/FPT.2018.00050 ©2018 IEEE


Joseph, J. M., Blochwitz, C., García-Ortiz, A. and Pionteck, T.: Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs, in Microprocessors and Microsystems, Vol. 48, pp. 36-47, 2017, 10.1016/j.micpro.2016.09.011


Joseph, J. M., Bamberg, L., Wrieden, S., Ermel, D., García-Oritz, A. and Pionteck, T.: Design method for asymmetric 3D interconnect architectures with high level models, in 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-8, 2017, 10.1109/ReCoSoC.2017.8016143 ©2017 IEEE


Drewes, T., Joseph, J. M. and Pionteck, T.: An FPGA-based prototyping framework for Networks-on-Chip, in International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-7, 2017, 10.1109/RECONFIG.2017.8279775 ©2017 IEEE


Joseph, J. M., Mey, M., Ehlers, K., Blochwitz, C., Winker, T. and Pionteck, T.: Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS, in International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-8, 2017, 10.1109/RECONFIG.2017.8279785 ©2017 IEEE


Blochwitz, C., Klink, R., Joseph, J. M. and Pionteck, T.: Continuous live-tracing as debugging approach on FPGAs, in International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-8, 2017, 10.1109/RECONFIG.2017.8279783 ©2017 IEEE


Joseph, J. M., Wrieden, S., Blochwitz, C., García-Oritz, A. and Pionteck, T.: A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip, in 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-8, 2016, 10.1109/ReCoSoC.2016.7533908 ©2016 IEEE


Joseph, J. M., Blochwitz, C. and Pionteck, T.: Adaptive allocation of default router paths in Network-on-Chips for latency reduction, in International Conference on High Performance Computing Simulation (HPCS), pp. 140-147, 2016, 10.1109/HPCSim.2016.7568328 ©2016 IEEE


Joseph, J. M., Winker, T., Ehlers, K., Blochwitz, C. and Pionteck, T.: Hardware-accelerated pose estimation for embedded systems using Vivado HLS, in International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-7, 2016, 10.1109/ReConFig.2016.7857173 ©2016 IEEE


Joseph, J. M., Blochwitz, C., Pionteck, T. and García-Ortiz, A.: Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), pp. 1-4, 2015, 10.1109/NORCHIP.2015.7364370 ©2015 IEEE


Blochwitz, C., Joseph, J. M., Backasch, R., Pionteck, T., Werner, S., Heinrich, D. and Groppe, S.: An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases, in International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-7, 2015, 10.1109/ReConFig.2015.7393291 ©2015 IEEE