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Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips

Authors:: Joseph, J. M. , Ermel, D. , Drewes, T. , Bamberg, L. , García-Ortiz, A. , Pionteck, T.
Book Title:: 8th International Conference on Modern Circuits and Systems Technologies (MOCAST)
Pages:: p.p. 1-4
Date:: 2019
DOI:: 10.1109/MOCAST.2019.8742035
hsb:: RWTH-2021-00466
Language:: English
Abstract:: Linear models are regularly used for mapping cores to tiles in a chip. System-on-Chip (SoC) design requires integration of functional units with varying sizes, but conventional models only account for identical-sized cores. Linear models cannot calculate the varying areas of cores in SoCs directly and must rely on approximations. We propose using non-linear models: Semi-definite programming (SDP) allows easy model definitions and achieves approximately 20% reduced area and up to 80% reduced white space. As computational time is similar to linear models, they can be applied, practically.
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