LISA

The Language for Instruction Set Architectures

LISA is a language which aims at the formal description of programmable architectures, their peripherals, and external interfaces. The language elements of LISA enable the description of different aspects of processor architectures like behavior, instruction set coding and syntax. All components of the target system can be desribed in an uniform manner. The language LISA and its generic machine model are able to produce bit- and cycle/phase-accurate models of systems that consist of programmable architectures and peripheral hardware compoments which include the effects of pipelining, interrupts, and interfacing. Such a LISA description can serve as an non-ambiguous specification which is exchanged between designers of processors, software development tools, and designers of hardware/software systems. 

Advances in semiconductor technology causing higher integration and thus increasing miniaturization have led to a shift from using distributed hardware components towards heterogeneous system-on-chip (SOC) designs. As the complexity and flexibility of the overall system become the key problems in SOC design, a growing amount of system functions and signal processing algorithms are implemented in software rather than in hardware by employing highly application specific programmable processor cores. The development of these
application specific instruction set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise knowledge in different domains: 

 

  1. application software development tools

  2. processor hardware implementation, and 

  3. system integration and verification

The LISA Processor Design Platform (LPDP) tool-suite is based on the machine description LISA. Starting from architecture descriptions in the LISA language, software development tools can be generated including 

  • HLL C-compiler, 

  • assembler, 

  • linker, 

  • simulator,

  • debugger frontend.


Moreover, synthesizable HDL (VHDL, Verilog, SystemC) code can be generated which can be processed by the standard synthesis tools. to enable easy integration into system simulation environments, the generated simulators offer a well defined API allowing access to the processor resources and control of the simulator run.

Publications

Hadaschik, N., Zakia, I., Ascheid, G. and Meyr, H.: Joint narrowband interference detection and channel estimation for wideband OFDM, in Proceedings of the European Wireless Conference 2007(Paris, France), Apr. 2007


Chattopadhyay, A., Ahmed, W., Karuri, K., Kammler, D., Leupers, R., Ascheid, G. and Meyr, H.: Design Space Exploration of Partially Re-configurable Embedded Processors, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Nice, France), pp. 319--324, Apr. 2007


Hadaschik, N., Ascheid, G. and Meyr, H.: Achievable Data Rate of Wideband OFDM with Data-Aided Channel Estimation, in IEEE International Symposion on Personal, Indoor and Mobile Radio Communications(Helsinki, Finland), Sep. 2006


Kempf, T., Adrat, M., Witte, E. M., Ramakrishnan, V., Antweiler, M. and Ascheid, G.: On the Feasibility of Implementing a Waveform Application onto a Given SDR Platform, in Military CIS Conference 2006 (MCC2006) (formerly NATO RCMCIS)(Gdynia, Poland), Sep. 2006


Steinert, W., Friederichs, L., Godtmann, S., Pollok, A., Hadaschik, N., Ascheid, G. and Meyr, H.: A Least-Squares Based Data-Aided Algorithm for Carrier Frequency Estimation, in IST Mobile & Wireless Communication Summit(Myconos, Greece), in IST Mobile & Wireless Communication Summit(Myconos, Greece), Jun. 2006


Scharwächter, H., Hohenauer, M., Leupers, R., Ascheid, G. and Meyr, H.: An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006


Angiolini, F., Ceng, J., Leupers, R., Ferrari, F., Ferri, C. and Benini, L.: An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration, in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006


Godtmann, S., Pollok, A., Hadaschik, N., Steinert, W., Ascheid, G. and Meyr, H.: Joint Iterative Synchronization and Decoding Assisted by Pilot Symbols, in IST Mobile & Wireless Communication Summit(Myconos, Greece), in IST Mobile & Wireless Communication Summit(Myconos, Greece), Jun. 2006


Karuri, K., Leupers, R., Ascheid, G., Meyr, H. and Kedia, M.: Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006


Leupers, R., Karuri, K., Kraemer, S. and Pandey, M.: A Design Flow for Configurable Embedded Processors based on Optimized Instruction Set Extension Synthesis, in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006


Kempf, T., Witte, E. M., Schliebusch, O., Ascheid, G., Adrat, M. and Antweiler, M.: A Concept for Waveform Description based SDR Implementation, in 4th Karlsruhe Workshop on Software Radios (WSR'06)(Karlsruhe, Germany), in 4th Karlsruhe Workshop on Software Radios (WSR'06)(Karlsruhe, Germany), Mar. 2006


Chattopadhyay, A., Geukes, B., Kammler, D., Witte, E. M., Schliebusch, O., Ishebabi, H., Leupers, R., Ascheid, G. and Meyr, H.: Automatic ADL-based Operand Isolation for Embedded Processors, in Design, Automation & Test in Europe (DATE)(Munich, Germany), pp. 600--605, Mar. 2006


Chattopadhyay, A., Kammler, D., Witte, E. M., Schliebusch, O., Ishebabi, H., Geukes, G., Leupers, R., Ascheid, G. and Meyr, H.: Automatic Low Power Optimizations during ADL-driven ASIP Design, in Proceedings of the International Symposium on VLSI Design, Automation & Test (VLSI-DAT)(Hsinchu, Taiwan), pp. 123--126, Apr. 2006


Ishebabi, H., Ascheid, G., Meyr, H., Atak, O., Atalar, A. and Arikan, E.: An Efficient Parallelization Technique for High Throughput FFT-ASIPs, in Proceedings of the 2006 International Symposium on Circuits and Systems(Kos, Greece), May. 2006


Meyr, H., Schliebusch, O., Wieferink, A., Kammler, D., Witte, E. M., Lüthje, O., Hohenauer, M., Braun, G. and Chattopadhyay, A.: Designing and Modeling MPSoC Processors and Communication Architectures, in Building ASIPs: The Mescal Methodology, Springer, pp. 229-280, Jun. 2005, ISBN: 0-387-26057-9


Ceng, J., Sheng, W., Hohenauer, M., Leupers, R., Ascheid, G., Meyr, H. and Braun, G.: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting, in SAMOS(Samos, Greece), in SAMOS(Samos, Greece), pp. 463-473, Jul. 2004


Witte, E. M., Chattopadhyay, A., Schliebusch, O., Kammler, D., Leupers, R., Ascheid, G. and Meyr, H.: Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation, in Proceedings of the International Conference on Computer Design (ICCD)(San Jose, California, USA), pp. 193--199, Oct. 2005


Nicola, M., Masera, G., Zamboni, M., Ishebabi, H., Kammler, D., Ascheid, G. and Meyr, H.: FFT processor: a case study in ASIP development, in Proceedings of the IST Mobile & Wireless Communications Summit(Dresden, Germany), Jun. 2005


Ceng, J., Hohenauer, M., Leupers, R., Ascheid, G., Meyr, H. and Braun, G.: C Compiler Retargeting Based on Instruction Semantics Models., in DATE(Munich, Germany), in DATE(Munich, Germany), Mar. 2005


Kempf, T., Karuri, K., Wallentowitz, S., Ascheid, G., Leupers, R. and Meyr, H.: A SW performance estimation framework for early System-Level-Design using fine-grained instrumentation, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006


Mozumdar, M., Karuri, K., Chattopadhyay, A., Kraemer, S., Scharwächter, H., Meyr, H., Ascheid, G. and Leupers, R.: Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study, in IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)(Samos, Greece), Jul. 2005


Schliebusch, O., Chattopadhyay, A., Witte, E. M., Kammler, D., Ascheid, G., Leupers, R. and Meyr, H.: Optimization Techniques for ADL-driven RTL Processor Synthesis, in Proceedings of the IEEE International Workshop on Rapid Systems Prototyping (RSP)(Montreal, Canada), pp. 165--171, Jun. 2005


Schliebusch, O., Chattopadhyay, A., Kammler, D., Witte, E. M., Leupers, R., Ascheid, G. and Meyr, H.: Prozessoren Maßgeschneidert, in Design & Elektronik 09/2004, 2004, ISSN: 0933-8667


Wieferink, A., Michiels, T., Nohl, A., Kogel, T., Leupers, R., Ascheid, G. and Meyr, H.: Retargetable Generation of TLM Bus Interfaces for MP-SoC Platforms, in 3rd IEEE/ACM/IFIP International Conference on HW/SW Codesign and System Synthesis (CODES+ISSS)(Jersey City, NJ, USA), in 3rd IEEE/ACM/IFIP International Conference on HW/SW Codesign and System Synthesis (CODES+ISSS)(Jersey City, NJ, USA), Sep. 2005


Senst, A., Schulz-Rittich, P., Ascheid, G. and Meyr, H.: Proportional Fair Multibeam Scheduling with Opportunistic Beamforming for Broadcast Channels, in 42nd Annual Allerton Conference on Communications, Control and Computing(Monticello, IL, USA), in 42nd Annual Allerton Conference on Communications, Control and Computing(Monticello, IL, USA), Oct. 2004


Schliebusch, O., Chattopadhyay, A., Kammler, D., Ascheid, G., Leupers, R., Meyr, H. and Kogel, T.: A Framework for Automated and Optimized ASIP Implementation Supporting Multiple Hardware Description Languages, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC)(Shanghai, China), pp. 280--285, Jan. 2005


Schliebusch, O., Kammler, D., Chattopadhyay, A., Leupers, R., Ascheid, G. and Meyr, H.: JTAG Interface and Debug Mechanism Generation for Automated ASIP Design, in Proceedings of the Global Signal Processing Expo and Conference (GSPx)(Santa Clara, CA, USA), Sep. 2004


Senst, A., Schulz-Rittich, P., Ascheid, G. and Meyr, H.: On the Throughput of Proportional Fair Scheduling with Opportunistic Beamforming for Continuous Fading States, in IEEE Vehicular Technology Conference (VTC-Fall)(Los Angeles, California), in IEEE Vehicular Technology Conference (VTC-Fall)(Los Angeles, California), 2004


Scharwächter, H., Kammler, D., Wieferink, A., Hohenauer, M., Karuri, K., Zeng, J., Leupers, R., Ascheid, G. and Meyr, H.: ASIP Architecture Exploration for Efficient IPSec Encryption: A Case Study, in Software and Compilers for Embedded Systems(Amsterdam, Netherlands), pp. 33--46, Springer Berlin/Heidelberg, Sep. 2004


Schmitt, L., Grundler, T., Schreyoegg, C., Ascheid, G. and Meyr, H.: Performance of Initial Synchronization Schemes for W-CDMA Systems with Spatio-Temporal Correlations, in IEEE International Conference on Communications (ICC)(Paris, France), in IEEE International Conference on Communications (ICC)(Paris, France), Jun. 2004


Lorenz, M., Marwedel, P., Dräger, T., Fettweis, G. and Leupers, R.: Compiler Based Exploration of DSP Energy Savings by SIMD Operations, in Asia South Pacific Design Automation Conference (ASP-DAC)(Yokohama,Japan), in Asia South Pacific Design Automation Conference (ASP-DAC)(Yokohama,Japan), Jan. 2004


Wieferink, A., Kogel, T., Hoffmann, A., Zerres, O. and Nohl, A.: SoC Integration of Programmable Cores, in International Workshop on IP-Based SoC Design(Grenoble, France), Nov. 2003


Wieferink, A., Kogel, T., Braun, G., Nohl, A., Leupers, R., Ascheid, G. and Meyr, H.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Paris, France), Feb. 2004


Schmitt, L., Simon, V., Grundler, T., Schreyoegg, C. and Meyr, H.: Initial Synchronization of W-CDMA Systems using a Power-Scaled Detector with Antenna Diversity in Frequency-Selective Rayleigh Fading Channels, in IEEE Global Communications Conference (GLOBECOM)(San Francisco, CA, USA), Dec. 2003


Leupers, R.: Digitale Signalprozessoren/Umsetzung von DSP-Algorithmen, in C.Siemers, A. Sikora (eds) Taschenbuch Digitaltechnik, in C.Siemers, A. Sikora (eds) Taschenbuch Digitaltechnik, Hanser - Verlag, ISBN 3-446-21862-9, 2002


Leupers, R., Wahlen, O., Hohenauer, M., Kogel, T. and Marwedel, P.: An Executable Intermediate Representation for Retargetable Compilation and High-Level Code Optimization, in Int. Workshop on Systems, Architecturs, Modeling and Simulation(SAMOS)(Samos(Greece)), in Int. Workshop on Systems, Architecturs, Modeling and Simulation(SAMOS)(Samos(Greece)), Jul. 2003


Wieferink, A., Kogel, T., Nohl, A., Hoffmann, A., Leupers, R. and Meyr, H.: A Generic Toolset for SoC Multiprocessor Debugging and Synchronisation, in IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)(The Hague (Netherlands)), Jun. 2003


Leupers, R.: Offset Assignment Showdown:Evaluation of DSP Adress Code Optimization Algorithms, in 12th International Conf.on Compiler Construction (CC)(Warsaw, Poland), in 12th International Conf.on Compiler Construction (CC)(Warsaw, Poland), Apr. 2003


Braun, G., Wieferink, A., Schliebusch, O., Leupers, R., Meyr, H. and Nohl, A.: Processor/Memory Co-Exploration on Multiple Abstraction Levels, in DesignAutomation&Test in Europe (Date)(Munich), in DesignAutomation&Test in Europe (Date)(Munich), Mar. 2003


Fechtel, S. A., Fock, G. and Speth, M.: Design of a OFDM-Receiver for DVB-T, Feb. 1997


Lorenz, M. and Dräger, T.: Energy Aware Compilation for DSPs with SIMDI Instructions, Jun. 2002


Schliebusch, O., Chattopadhyay, A., Steinert, M., Braun, G., Nohl, A., Leupers, R., Ascheid, G. and Meyr, H.: RTL Processor Synthesis for Architecture Exploration and Implementation, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE) - Designers Forum(Paris, France), Feb. 2004


Hoffmann, A., Kogel, T., Nohl, A., Braun, G., Schliebusch, O., Wahlen, O., Wieferink, A. and Meyr, H.: A Novel Methodology for the Design of Application Specific Instruction-Set Processor Using a Machine Description Language, in IEEE Transactions on Computer-Aided Design of Integrated Cicuits and Systems (TCAD) vol. 20 no. 11, pp. 1338-1354, Nov. 2001


Kogel, T., Leupers, R. and Meyr, H.: Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms, Springer, Jun. 2006, ISBN: 1-402-04825-4, 10.1007/1-4020-4826-2


Leupers, R.: Genetic Algorithm based DSP Code Optimization, in Drechsler, R. and Drechsler, S. (eds.):Evolutionary Algorithms for Embedded System Design, in Drechsler, R. and Drechsler, S. (eds.):Evolutionary Algorithms for Embedded System Design, Kluwer Academic Publishers, ISBN 1-4020-7276-7, Nov. 2002


Glökler, T. and Meyr, H.: ASIP Design and the Energy-Flexibility Tradeoff, in Proceedings of the 10th Aachen Symposium on Signal Theory, ISBN 3-8007-2610-6(Aachen, Germany), in Proceedings of the 10th Aachen Symposium on Signal Theory, ISBN 3-8007-2610-6(Aachen, Germany), pp. 343-348, Sep. 2001


Zivojnovic, V., Pees, S., Schläger, C., Willems, M., Schoenen, R. and Meyr, H.: LISA - Beschreibungssprache und Generisches Maschinenmodel für das HW/SW Co-Design, in DSP Deutschland (DSP D), Oct. 1996


Kogel, T., Wieferink, A., Meyr, H. and Kroll, A.: SystemC based Architecture Exploration of a 3D Graphic Processor, in IEEE Workshop on Signal Processing Systems (SIPS)(Antwerp (Belgium)), Sep. 2001


Keding, H., Coors, M., Lüthje, O. and Meyr, H.: Fast Bit-True Simulation, in Proceedings of the Design Automation Conference (DAC)(Las Vegas, Nevada), in Proceedings of the Design Automation Conference (DAC)(Las Vegas, Nevada), Jun. 2001


Hoffmann, A., Schliebusch, O., Nohl, A., Braun, G. and Meyr, H.: A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using the Machine Description Language LISA, in Proceedings of the International Conference on Computer Aided Design (ICCAD)(San Jose, USA), Nov. 2001 ©2001 IEEE


Baltersee, J., Fock, G. and Meyr, H.: Achievable Rate of MIMO Channels with Data-Aided Channel Estimation, in Proceedings of the IEEE Information Theory Workshop(Cairns, Australia), in Proceedings of the IEEE Information Theory Workshop(Cairns, Australia), Sep. 2001


Hoffmann, A., Nohl, A., Braun, G. and Meyr, H.: A Survey on Modeling Issues Using the Machine Description Language LISA, in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP)(Salt Lake City), in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP)(Salt Lake City), May. 2001


Baltersee, J., Fock, G., Schulz-Rittich, P. and Meyr, H.: Performance Analysis of Phasor Estimation Algorithms for a FDD-UMTS RAKE Receiver, in Proceedings of the IEEE Sixth International Symposium on Spread Spectrum Techniques & Applications ISSSTA(Parsippany), Sep. 2000


Hoffmann, A., Nohl, A., Braun, G., Wahlen, O. and Meyr, H.: Modeling and Simulation Issues of Programmable Architectures, in Proceedings of the 4th workshop on Software & Compilers for Embedded Systems (SCOPES)(St. Goar), in Proceedings of the 4th workshop on Software & Compilers for Embedded Systems (SCOPES)(St. Goar), Mar. 2001


Schlebusch, H. J.: Nonlinear importance sampling techniques for efficient simulation of communication systems, in IEEE Int. Conf. Commun., ICC'90(Atlanta, GA, USA), in IEEE Int. Conf. Commun., ICC'90(Atlanta, GA, USA), Apr. 1990


Pankert, M. and Mauss, O.: DSP-Implementierung eines Spread-Spectrum-Empfängers mit Hilfe von High Level Codesynthese, in Anwendung moderner Simulationswerkzeuge in der Nachrichten- und Kommunikationstechnik, 1993


Keding, H., Hürtgen, F., Willems, M. and Coors, M.: Transformation of Floating-Point into Fixed-Point Algorithms by Interpolation Applying a Statistical Approach, in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(Toronto), in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(Toronto), Sep. 1998


Pankert, M., Mauss, O. and Meyr, H.: Computer Aided Design of a DSP-Based Slow Frequency Hopping MFSK Receiver, in SITEL/IEEE Benelux One Day Conference: New Radiocommunications Services and their Regulatory Aspects(Brussels), in SITEL/IEEE Benelux One Day Conference: New Radiocommunications Services and their Regulatory Aspects(Brussels), Apr. 1994


Pees, S., Zivojnovic, V., Hoffmann, A. and Meyr, H.: Retargetable Timed Instruction Set Simulation of Pipelined Processor Architectures, in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(Toronto), pp. 595-599, Sep. 1998


Schläger, C. and Zivojnovic, V.: C/C++ - Based Techniques for Production-Quality DSP Code Development, in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(Boston), Oct. 1995


Hoffmann, A., Pees, S. and Meyr, H.: A Retargetable Tool-suite for Exploration of Programmable Architectures in SOC-Design, in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(Orlando), in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(Orlando), pp. 595-599, Nov. 1999


Zivojnovic, V., Pees, S., Schläger, C., Willems, M., Schoenen, R. and Meyr, H.: LISA - Machine Description Language and Generic Machine Model, in International Conference on Signal Processing Applications and Technology (ICSPAT) (Boston), Oct. 1996


Zivojnovic, V., Pees, S., Schläger, C. and Meyr, H.: LISA bridges gaps in high-tech languages, in Electronic Engineering Times, Oct. 1996


Murillo, L. G., Harnath, J., Leupers, R. and Ascheid, G.: Scalable and Retargetable Debugger Architecture for Heterogeneous MPSoCs, in System, Software, SoC and Silicon Debug Conference (S4D), Vienna, Austria, Sep. 2012, ISBN: 978-1-46732-454-0, ISSN: 2114-3684 ©2012 IEEE


Processor Description Language 
for Architecture Exploration, Implementation and 
System Level Simulation

Contact

Anupam Chattopadhyay, Felix Engel, Manuel Hohenauer, David Kammler, Ernst Martin Witte, Gunnar Braun, Andreas Hoffmann, Tim Kogel, Achim Nohl, Andreas Ropers, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink