Institute for Communication Technologies and Embedded Systems

Telecommunication products such as networking devices, cellular phones, and modems are rapidly growing in complexity. Due to the fierce competition with an increased number of competitors in this field, time-to-market is particularly critical. Because of these reasons combined with product performance/size issues, system designers are forced to increasingly use embedded processors.

The design and implementation of an embedded processor, such as a DSP device embedded in a cellular phone, requires the following tasks or phases:

  • Architecture exploration.

  • Architecture implementation.

  • Application software design.

  • System integration and verification.

During the architecture exploration phase, software development tools (i.e. HLL compiler, assembler, linker, and cycle accurate simulator) are required to profile and benchmark the target application on different architecture alternatives. This process is usually an iterative one that is repeated until a best fit between selected architecture and target application is obtained. Every change to the architecture specification requires a complete new set of software development tools. As these changes on the tools are carried out mainly manually, this results in a long, tedious and extremely error-prone process. Moreover, the lack of automation makes it very difficult to match the profiling tools to an abstract specification of the target architecture.

In the architecture implementation phase, the chosen architecture design is used as the basis for synthesizing the specified processor. At this point, a hardware description language such as VHDL or Verilog is introduced. With this additional manual transformation it is quite obvious that considerable consistency problems arise between the architecture specification, the software development tools, and the hardware implementation.

During the software application design phase, software designers need a set of production-quality software development tools. Since the demands of the software application designer and the hardware processor designer place different requirements on software development tools, new tools are required. For example, the processor designer needs a cycle/phase accurate simulator for hardware/ software partitioning and profiling, which is very accurate but inevitably slow, whereas the application designer needs more simulation speed than accuracy. At this point, the complete software development tool-suite is usually re-implemented by hand - consistency problems are self-evident.

In the system integration and verification phase, the major task is to evaluate the trade-off between various functionalities (e.g. speed, size, and power consumption) to determine which part of the overall system functionality should be implemented in software and which must be implemented in hardware (hardware-software partitioning). Here, co-simulation interfaces must be developed to integrate the software simulator for the chosen architecture into a system simulation environment. These interfaces vary with the architecture that is currently under test. Again, manual modification of the interfaces is required with each change of the architecture.


The language elements of LISA can be used to describe various aspects of processor architectures including behavior, instruction set coding and syntax. All components of the target systems are described in a uniform manner using a syntax that is very similar to the C programming language. LISA and its generic machine model can produce bit-accurate and cycle/phase accurate models that consist of programmable architectures and peripheral hardware components, including the effects of pipelining, interrupts, and interfacing. The LISA processor design platform (LPDP) is an environment that allows the automatic generation of software development tools for architecture exploration, hardware implementation, software development tools for application design, and hardware-software co-simulation interfaces from one sole specification of the target architecture in the LISA language. Figure 1 shows the components of the LPDP environment. The set of LPDP tools and their areas of application are as follows:

  • Hardware Designer Platform - for exploration and processor generation.

    The development of a new architecture always starts in software with an abstract model of the target architecture to be implemented. Using the LISA language to specify the structure, the behavior, and the instruction-set in a uniform and clear manner, the following flow is used to explore and create the processor.

The design of a new architecture requires the designer to work in two fields: on the one hand the development of the software part including compiler, assembler, linker and simulator and on the other hand the development of the target architecture itself. The software simulator produces profiling data and thus may answer questions concerning the instruction set, the performance of an algorithm and the required size of memory and registers. Statements on the need of silicon area or power consumption can only be given in conjunction with a synthesizable HDL model. The LISA hardware designer platform can synthesize the following tools: 

  • LISA language debugger for debugging the instruction-set as well as the behavior with a dedicated graphical debugger frontend. The debugger visualizes the assembling/disassembling process as well as the execution of instructions and enables the model designer to quickly detect errors in the processor description. It is comparable in its functioning with a graphical debugger as it is commonly used for C/C++ debugging as e.g. ddd.

  • LISA  exploration assembler lasm. The LISA assembler translates meaningful text-based instructions into object code for the respective programmable architecture.

  • LISA exploration linker with backend for COFF (Common Object File Format).

  • LISA instruction-set architecture (ISA) simulator for cycle accurate simulation including support for deep instruction and data pipelines. In exploration, for flexibility reasons, the simulator is working with the interpretive simulation technology.

Besides the ability to synthesize a complete set of software development tools, synthesizable HDL code (both VHDL and Verilog) for the processor`s control path and instruction decoder can be generated automatically from the LISA processor description. This also comprises the complete pipeline and pipeline controller including complex interlocking mechanisms, forwarding, etc.

Since both the software development tools as well as the HDL model are derived from one sole specification of the target architecture in the LISA language, the tools are 100% consistent with the HDL code and correct by construction. There is no need to verify them against the original architecture specification.

  • Software Designer Platform - for software application design.

    To cope with the requirements of functionality and speed in the software design phase, the tools generated for this purpose are an enhanced version of the tools generated during architecture exploration phase. The generated simulation tools are enhanced in speed by applying the compiled simulation principle - where applicable -- and are faster by one to two orders in magnitude than the tools currently provided by architecture vendors such as Texas Instruments. An overview of the generated tools for application software design is given in the following figure.


As the compiled simulation principle requires the program memory not to be modified during the simulation run, this holds true for most DSPs. However, for architectures running the program from external memory or working with operating systems which load/unload applications to/from internal program memory, this simulation technique is not suitable. For this purpose, an interpretive simulator is provided.

  • System Integrator Platform - for system integration and verification.

    Once the processor software simulator is available, it must be integrated and verified in the context of the whole system (SOC) which is includes a mixture of different EPs, memories, and interconnect components. Verification of the complete system, including software, has become the critical bottleneck in the design process of SOC. Due to the diversity of EP sources, hardware-software co-simulation integrates hardware and software design techniques that incorporate the use of various languages (VHDL, Verilog, C/C++), formalisms, and tools.

    In order to support the system integration and verification, the LPDP system integrator platform provides a well defined application programmer interface (API) to interconnect the instruction-set simulator generated from the LISA specification with other simulators. The API allows to control the simulator by stepping, running, and setting breakpoints in the application code and by providing access to the processor resources.