Institute for Communication Technologies and Embedded Systems

LISA

The Language for Instruction Set Architectures

LISA is a language which aims at the formal description of programmable architectures, their peripherals, and external interfaces. The language elements of LISA enable the description of different aspects of processor architectures like behavior, instruction set coding and syntax. All components of the target system can be desribed in an uniform manner. The language LISA and its generic machine model are able to produce bit- and cycle/phase-accurate models of systems that consist of programmable architectures and peripheral hardware compoments which include the effects of pipelining, interrupts, and interfacing. Such a LISA description can serve as an non-ambiguous specification which is exchanged between designers of processors, software development tools, and designers of hardware/software systems. 

Advances in semiconductor technology causing higher integration and thus increasing miniaturization have led to a shift from using distributed hardware components towards heterogeneous system-on-chip (SOC) designs. As the complexity and flexibility of the overall system become the key problems in SOC design, a growing amount of system functions and signal processing algorithms are implemented in software rather than in hardware by employing highly application specific programmable processor cores. The development of these
application specific instruction set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise knowledge in different domains: 

 

  1. application software development tools

  2. processor hardware implementation, and 

  3. system integration and verification

The LISA Processor Design Platform (LPDP) tool-suite is based on the machine description LISA. Starting from architecture descriptions in the LISA language, software development tools can be generated including 

  • HLL C-compiler, 

  • assembler, 

  • linker, 

  • simulator,

  • debugger frontend.


Moreover, synthesizable HDL (VHDL, Verilog, SystemC) code can be generated which can be processed by the standard synthesis tools. to enable easy integration into system simulation environments, the generated simulators offer a well defined API allowing access to the processor resources and control of the simulator run.

Processor Description Language 
for Architecture Exploration, Implementation and 
System Level Simulation

Contact

Anupam Chattopadhyay, Felix Engel, Manuel Hohenauer, David Kammler, Ernst Martin Witte, Gunnar Braun, Andreas Hoffmann, Tim Kogel, Achim Nohl, Andreas Ropers, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink

Publications

Chattopadhyay, A., Ahmed, W., Karuri, K., Kammler, D., Leupers, R., Ascheid, G. and Meyr, H.: Design Space Exploration of Partially Re-configurable Embedded Processors, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Nice, France), pp. 319--324, Apr. 2007
Chattopadhyay, A., Zhang, D., Kammler, D., Witte, E. M., Leupers, R., Ascheid, G. and Meyr, H.: Power-efficient Instruction Encoding Optimization for Embedded Processors, in Proceedings of the International Conference on VLSI Design (VLSID)(Bangalore, India), pp. 595--600, Jan. 2007
Chattopadhyay, A., Kammler, D., Zhang, D., Ascheid, G., Leupers, R. and Meyr, H.: Specification-driven Exploration and Implementation of Partially Re-configurable Processors, in Proceedings of the Global Signal Processing Expo and Conference (GSPx)(Santa Clara, California, USA), Oct. 2006
Saponara, S., Fanucci, L., Marsi, S., Ramponi, G., Witte, E. M. and Kammler, D.: Design of Application Specific Instruction-Set Processor for Image and Video Filtering, in Proceedings of European Signal Processing Conference (EUSIPCO)(Florence, Italy), Sep. 2006
Chattopadhyay, A., Sinha, A., Zhang, D., Leupers, R., Ascheid, G. and Meyr, H.: Integrated Verification Approach during ADL-driven Processor Design, in IEEE International Workshop on Rapid System Prototyping (RSP)(Chania, Crete), in IEEE International Workshop on Rapid System Prototyping (RSP)(Chania, Crete), Jun. 2006
Ishebabi, H., Ascheid, G., Meyr, H., Atak, O., Atalar, A. and Arikan, E.: An Efficient Parallelization Technique for High Throughput FFT-ASIPs, in Proceedings of the 2006 International Symposium on Circuits and Systems(Kos, Greece), May. 2006
Atak, O., Atalar, A., Arikan, E., Ishebabi, H., Kammler, D., Ascheid, G., Meyr, H., Nicola, M., Masera, G. and Zamboni, M.: Design of Application Specific Processors for the Cached FFT Algorithm, in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP)(Toulouse, France), pp. 1028--1031, May. 2006
Chattopadhyay, A., Kammler, D., Witte, E. M., Schliebusch, O., Ishebabi, H., Geukes, G., Leupers, R., Ascheid, G. and Meyr, H.: Automatic Low Power Optimizations during ADL-driven ASIP Design, in Proceedings of the International Symposium on VLSI Design, Automation & Test (VLSI-DAT)(Hsinchu, Taiwan), pp. 123--126, Apr. 2006
Scharwächter, H., Hohenauer, M., Leupers, R., Ascheid, G. and Meyr, H.: An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Angiolini, F., Ceng, J., Leupers, R., Ferrari, F., Ferri, C. and Benini, L.: An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration, in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Fanucci, L., Cassiano, M., Saponara, S., Kammler, D., Witte, E. M., Schliebusch, O., Ascheid, G., Leupers, R. and Meyr, H.: ASIP Design and Synthesis for Non Linear Filtering in Image Processing, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Munich, Germany), pp. 233--238, Mar. 2006
Karuri, K., Leupers, R., Ascheid, G., Meyr, H. and Kedia, M.: Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Leupers, R., Karuri, K., Kraemer, S. and Pandey, M.: A Design Flow for Configurable Embedded Processors based on Optimized Instruction Set Extension Synthesis, in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Kempf, T., Witte, E. M., Schliebusch, O., Ascheid, G., Adrat, M. and Antweiler, M.: A Concept for Waveform Description based SDR Implementation, in 4th Karlsruhe Workshop on Software Radios (WSR'06)(Karlsruhe, Germany), in 4th Karlsruhe Workshop on Software Radios (WSR'06)(Karlsruhe, Germany), Mar. 2006
Chattopadhyay, A., Geukes, B., Kammler, D., Witte, E. M., Schliebusch, O., Ishebabi, H., Leupers, R., Ascheid, G. and Meyr, H.: Automatic ADL-based Operand Isolation for Embedded Processors, in Design, Automation & Test in Europe (DATE)(Munich, Germany), pp. 600--605, Mar. 2006
Kempf, T., Karuri, K., Wallentowitz, S., Ascheid, G., Leupers, R. and Meyr, H.: A SW performance estimation framework for early System-Level-Design using fine-grained instrumentation, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Witte, E. M., Chattopadhyay, A., Schliebusch, O., Kammler, D., Leupers, R., Ascheid, G. and Meyr, H.: Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation, in Proceedings of the International Conference on Computer Design (ICCD)(San Jose, California, USA), pp. 193--199, Oct. 2005
Mozumdar, M., Karuri, K., Chattopadhyay, A., Kraemer, S., Scharwächter, H., Meyr, H., Ascheid, G. and Leupers, R.: Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study, in IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)(Samos, Greece), Jul. 2005
Karuri, K., Al Faruque, M. A., Kraemer, S., Leupers, R., Ascheid, G. and Meyr, H.: Fine-grained Application Source Code Profiling for ASIP Design, in 42nd Design Automation Conference(Anaheim, California, USA), Jun. 2005
Meyr, H., Schliebusch, O., Wieferink, A., Kammler, D., Witte, E. M., Lüthje, O., Hohenauer, M., Braun, G. and Chattopadhyay, A.: Designing and Modeling MPSoC Processors and Communication Architectures, in Building ASIPs: The Mescal Methodology, Springer, pp. 229-280, Jun. 2005, ISBN: 0-387-26057-9
Schliebusch, O., Chattopadhyay, A., Witte, E. M., Kammler, D., Ascheid, G., Leupers, R. and Meyr, H.: Optimization Techniques for ADL-driven RTL Processor Synthesis, in Proceedings of the IEEE International Workshop on Rapid Systems Prototyping (RSP)(Montreal, Canada), pp. 165--171, Jun. 2005
Nicola, M., Masera, G., Zamboni, M., Ishebabi, H., Kammler, D., Ascheid, G. and Meyr, H.: FFT processor: a case study in ASIP development, in Proceedings of the IST Mobile & Wireless Communications Summit(Dresden, Germany), Jun. 2005
Schliebusch, O., Ascheid, G., Wieferink, A., Leupers, R. and Meyr, H.: Application Specific Processors for Flexible Receivers, in Proc. of National Symposium of Radio Science (URSI)(Poznan (Poland)), in Proc. of National Symposium of Radio Science (URSI)(Poznan (Poland)), Apr. 2005
Ceng, J., Hohenauer, M., Leupers, R., Ascheid, G., Meyr, H. and Braun, G.: C Compiler Retargeting Based on Instruction Semantics Models., in DATE(Munich, Germany), in DATE(Munich, Germany), Mar. 2005
Schliebusch, O., Chattopadhyay, A., Kammler, D., Ascheid, G., Leupers, R., Meyr, H. and Kogel, T.: A Framework for Automated and Optimized ASIP Implementation Supporting Multiple Hardware Description Languages, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC)(Shanghai, China), pp. 280--285, Jan. 2005
Schliebusch, O., Kammler, D., Chattopadhyay, A., Leupers, R., Ascheid, G. and Meyr, H.: JTAG Interface and Debug Mechanism Generation for Automated ASIP Design, in Proceedings of the Global Signal Processing Expo and Conference (GSPx)(Santa Clara, CA, USA), Sep. 2004
Leupers, R., Dörper, M. and Wieferink, A.: Chips mit System, in c't 20/2004(Hannover, Germany), in c't 20/2004(Hannover, Germany), pp. 92-99, Heise Verlag, Sep. 2004
Scharwächter, H., Kammler, D., Wieferink, A., Hohenauer, M., Karuri, K., Zeng, J., Leupers, R., Ascheid, G. and Meyr, H.: ASIP Architecture Exploration for Efficient IPSec Encryption: A Case Study, in Software and Compilers for Embedded Systems(Amsterdam, Netherlands), pp. 33--46, Springer Berlin/Heidelberg, Sep. 2004
Ceng, J., Sheng, W., Hohenauer, M., Leupers, R., Ascheid, G., Meyr, H. and Braun, G.: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting, in SAMOS(Samos, Greece), in SAMOS(Samos, Greece), pp. 463-473, Jul. 2004
Wieferink, A., Dörper, M., Kogel, T., Leupers, R., Ascheid, G. and Meyr, H.: Early ISS Integration into Network-on-Chip Designs, in Int. Workshop on Systems, Architectures, Modeling and Simulation (SAMOS)(Samos (Greece)), in Int. Workshop on Systems, Architectures, Modeling and Simulation (SAMOS)(Samos (Greece)), Jul. 2004
Kogel, T. and Meyr, H.: Heterogeneous MP-SoC - The Solution to Energy-Efficient Signal Processing, in Design Automation Conference (DAC)(San Diego, USA), in Design Automation Conference (DAC)(San Diego, USA), Jun. 2004
Schliebusch, O., Chattopadhyay, A., Steinert, M., Braun, G., Nohl, A., Leupers, R., Ascheid, G. and Meyr, H.: RTL Processor Synthesis for Architecture Exploration and Implementation, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE) - Designers Forum(Paris, France), Feb. 2004
Hohenauer, M., Scharwächter, H., Karuri, K., Wahlen, O., Kogel, T., Leupers, R., Ascheid, G., Meyr, H. and Braun, G.: Compiler-in-loop Architecture Exploration for Efficient Application Specific Embedded Processor Design, in Design & Elektronik(Munich, Germany), WEKA Verlag, Feb. 2004
Hohenauer, M., Scharwächter, H., Karuri, K., Wahlen, O., Kogel, T., Leupers, R., Ascheid, G., Meyr, H., Braun, G. and van Someren, H.: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Paris, France), Feb. 2004
Wieferink, A., Kogel, T., Braun, G., Nohl, A., Leupers, R., Ascheid, G. and Meyr, H.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Paris, France), Feb. 2004
Schliebusch, O., Chattopadhyay, A., Kammler, D., Witte, E. M., Leupers, R., Ascheid, G. and Meyr, H.: Prozessoren Maßgeschneidert, in Design & Elektronik 09/2004, 2004, ISSN: 0933-8667
Leupers, R., Wahlen, O., Hohenauer, M., Kogel, T. and Marwedel, P.: An Executable Intermediate Representation for Retargetable Compilation and High-Level Code Optimization, in Int. Workshop on Systems, Architecturs, Modeling and Simulation(SAMOS)(Samos(Greece)), in Int. Workshop on Systems, Architecturs, Modeling and Simulation(SAMOS)(Samos(Greece)), Jul. 2003
Wieferink, A., Kogel, T., Nohl, A., Hoffmann, A., Leupers, R. and Meyr, H.: A Generic Toolset for SoC Multiprocessor Debugging and Synchronisation, in IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)(The Hague (Netherlands)), Jun. 2003
Nohl, A., Greive, V., Braun, G., Hoffmann, A., Leupers, R., Schliebusch, O. and Meyr, H.: Instruction Encoding Synthesis for Architecture Exploration using Hierarchical Processor Models, in 40th Design Automation Conference (DAC)(Anaheim (USA)), Jun. 2003
Braun, G., Wieferink, A., Schliebusch, O., Leupers, R., Meyr, H. and Nohl, A.: Processor/Memory Co-Exploration on Multiple Abstraction Levels, in DesignAutomation&Test in Europe (Date)(Munich), in DesignAutomation&Test in Europe (Date)(Munich), Mar. 2003
Wahlen, O., Hohenauer, M., Leupers, R. and Meyr, H.: Instruction Scheduler Generation for Retargetable Compilation, in IEEE Design&Test of Computers, in IEEE Design&Test of Computers, Jan. 2003
Hoffmann, A., Meyr, H. and Leupers, R.: Architecture Exploration for Embedded Processors with LISA, Kluwer Academic Press, Dec. 2002, ISBN: 1-402-07338-0, 10.1007/978-1-4757-4538-2
Wahlen, O., Hohenauer, M., Leupers, R. and Meyr, H.: Using Virtual Resources for Generating Instruction Schedulers, Nov. 2002 ©2002 IEEE
Nohl, A., Hoffmann, A., Leupers, R., Meyr, H. and Mayer, U.: Das Beste aus zwei Welten:Schnelle und flexible Prozessorsimulation mit Just-in Time Cache Compiled Simulation, in Elektronik, Nr.23(Munich (Germany)), in Elektronik, Nr.23(Munich (Germany)), Weka Verlag, Nov. 2002
Leupers, R., Kogel, T., Meyr, H., Hoffmann, A., Mayer, U., Buch, S. and Steinert, M.: Productivity Boost in Embedded Processor Design, in EDAVision Magazine, in EDAVision Magazine, Aug. 2002
Wahlen, O., Glökler, T., Nohl, A., Hoffmann, A., Leupers, R. and Meyr, H.: Application Specific Compiler/Architecture Codesign: A Case Study, Jun. 2002 ©2002 IEEE
Nohl, A., Braun, G., Hoffmann, A., Schliebusch, O., Leupers, R. and Meyr, H.: A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation, in Proceedings of the Design Automation Conference (DAC)(New Orleans), in Proceedings of the Design Automation Conference (DAC)(New Orleans), Jun. 2002
Schliebusch, O., Hoffmann, A., Nohl, A., Braun, G. and Meyr, H.: Architecture Implementation Using the Machine Description Language LISA, in Proceedings of the ASPDAC/VLSI Design(Bangalore, India), Jan. 2002
Leupers, R., Meyr, H., Hoffmann, A. and Mayer, U.: LISA macht die Tools, in Design und Elektronik, Vol. 5, 2002
Hoffmann, A., Kogel, T., Nohl, A., Braun, G., Schliebusch, O., Wahlen, O., Wieferink, A. and Meyr, H.: A Novel Methodology for the Design of Application Specific Instruction-Set Processor Using a Machine Description Language, in IEEE Transactions on Computer-Aided Design of Integrated Cicuits and Systems (TCAD) vol. 20 no. 11, pp. 1338-1354, Nov. 2001
Hoffmann, A., Schliebusch, O., Nohl, A., Braun, G. and Meyr, H.: A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using the Machine Description Language LISA, in Proceedings of the International Conference on Computer Aided Design (ICCAD)(San Jose, USA), Nov. 2001 ©2001 IEEE
Braun, G., Hoffmann, A., Nohl, A. and Meyr, H.: Using Static Scheduling Techniques for Retargeting of High Speed, Compiled Simulators for Embedded Processors from an Abstract Machine Description, in Proceedings of the International Symposium of System Synthesis (ISSS)(Montreal, Canada), in Proceedings of the International Symposium of System Synthesis (ISSS)(Montreal, Canada), Oct. 2001
Hoffmann, A., Nohl, A., Braun, G. and Meyr, H.: A Survey on Modeling Issues Using the Machine Description Language LISA, in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP)(Salt Lake City), in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP)(Salt Lake City), May. 2001
Hoffmann, A., Nohl, A., Braun, G., Wahlen, O. and Meyr, H.: Modeling and Simulation Issues of Programmable Architectures, in Proceedings of the 4th workshop on Software & Compilers for Embedded Systems (SCOPES)(St. Goar), in Proceedings of the 4th workshop on Software & Compilers for Embedded Systems (SCOPES)(St. Goar), Mar. 2001
Hoffmann, A., Nohl, A., Braun, G. and Meyr, H.: Generating Production Quality Software Development Tools Using a Machine Description Language, in Proceedings of the European Conference on Design Automation and Test Europe (DATE)(Munich), in Proceedings of the European Conference on Design Automation and Test Europe (DATE)(Munich), Mar. 2001
Hoffmann, A., Kogel, T. and Meyr, H.: A Framework for Fast Hardware-Software Co-simulation, in Proceedings of the European Conference on Design Automation and Test Europe (DATE)(Munich), in Proceedings of the European Conference on Design Automation and Test Europe (DATE)(Munich), Mar. 2001
Pees, S., Hoffmann, A. and Meyr, H.: Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language, in Proceedings of the European Conference on Design, Automation and Test (DATE)(Paris), Mar. 2000
Hoffmann, A., Pees, S. and Meyr, H.: A Retargetable Tool-suite for Exploration of Programmable Architectures in SOC-Design, in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(Orlando), in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(Orlando), pp. 595-599, Nov. 1999
Pees, S., Zivojnovic, V., Hoffmann, A. and Meyr, H.: Retargetable Timed Instruction Set Simulation of Pipelined Processor Architectures, in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(Toronto), pp. 595-599, Sep. 1998
Pees, S., Hoffmann, A. and Meyr, H.: Retargetable Timed Instruction Set Simulation of Pipelined DSP Architectures, in Proc. of DSP Deutschland 98, 1998
Pees, S., Vaupel, M., Zivojnovic, V. and Meyr, H.: On Core and More: A Design Perspective for Systems-on-a-Chip, in Proceedings of the IEEE International Conference on Application Specific Systems, Architectures, and Processors (ASAP), 1997
Zivojnovic, V., Pees, S., Schläger, C., Willems, M., Schoenen, R. and Meyr, H.: DSP Processor/Compiler Co-Design: A Quantitative Approach, in Proc. of the IEEE Symposium on System Synthesis - La Jolla, Nov. 1996
Zivojnovic, V., Pees, S., Schläger, C., Willems, M., Schoenen, R. and Meyr, H.: LISA - Machine Description Language and Generic Machine Model, in International Conference on Signal Processing Applications and Technology (ICSPAT) (Boston), Oct. 1996
Zivojnovic, V., Pees, S., Schläger, C., Willems, M., Schoenen, R. and Meyr, H.: LISA - Beschreibungssprache und Generisches Maschinenmodel für das HW/SW Co-Design, in DSP Deutschland (DSP D), Oct. 1996
Zivojnovic, V., Pees, S., Schläger, C. and Meyr, H.: LISA bridges gaps in high-tech languages, in Electronic Engineering Times, Oct. 1996