The HDL model can be generated in VHDL, Verilog and SystemC. Using the VHDL and Verilog description languages the following parts of the target architecture can be generated automatically:
Coarse processor structure, such as register set, pipeline, pipeline registers and test-interface.
Instruction decoder, setting control signals and data values which are carried through the pipeline and activate the respective functional units executed in context of the decoded instruction.
Pipeline controller, handling different kinds of hazards coursing pipeline interlocks, pipeline register Flushes and supporting mechanisms such as data forwarding.
Besides that, hardware operations as they are described in the LISA model can be grouped to functional units. Those functional units are synthesized as frames in case of VHDL and Verilog generation. Thus, i.e. the ports to the functional units as well as the interconnects to the pipeline registers and other functional units are automatically generated while the content needs to be filled manually with code.
If SystemC is chosen for HDL model generation the content of functional units can be additionally generated. Due to the behavior description in a LISA model is C-based the HDL generator can take full advantage of the SystemC modeling language. Therefore, the complete HDL model can be generated in SystemC.
Because of the flexibility of the LISA HDL generator the designer may concentrate onto his primary tasks and does not need to care about the error prone and long wired implementation of i.e. control path and decoder.