One of the main challenges of future design practice is the integration of point tools that address different areas of hardware and software design. Recent studies have shown that the digital system design industry loses approximately $4.5 billion each year in nonproductive time due to a lack of interoperable tools . The development and evaluation of algorithms and protocol specifications for broadband network components is carried out using high-level design tools, such as OPNET (Mil3) that provides the user with efficient capabilities to model and simulate communication networks. Common approaches to hardware implementation and verification, on the other hand, start at the VHDL level and are based on the creation of regression test benches to perform validation of timing and functionality by simulation. The time needed to develop test benches for VHDL simulations has proven to be a significant bottleneck (up to 50% of the design time). Furthermore, the use of different simulation tools at different levels of abstraction often leads to specification mismatches and inconsistencies between high-level representations and their implementations.
In order to overcome this verification gap it becomes necessary to provide an interface between high-level design tools such as OPNET and VHDL design tools such as Synopsys' VHDL System Simulator (VSS). Therefore, we developed an OPNET-VSS co-simulation that offers the following advantages:
- Functional verification of a VHDL model in the system environment.
- Reuse of existing test pattern from network simulations.
- Access to powerful analysis capabilities available in OPNET.
- Ability to model, simulate and analyze the system environment at the most appropriate level of abstraction.
- Support of iterations between system and implementation-level design tools to explore the design trade-offs.