The LISA language was designed to bridge the gap between hardware and software design - it provides the software developer with all required information for retargeting software development tools and enables the hardware designer to synthesize the architecture from the same specification. As we are targeting the development of application specific instruction set processors (ASIP), which are highly optimized for one specific application domain, the HDL code generated has to fulfill tight constraints to be an acceptable replacement for handwritten HDL code by experienced designers.
Because of an successive refinement of the LISA model the change from architecture exploration to implementation is floating. Thus, the design can be easily improved either on the LISA or HDL model level. Standard synthesis tools are used to synthesize the gate level model.
The HDL model can be generated in VHDL, Verilog and SystemC. Using the VHDL and Verilog description languages the following parts of the target architecture can be generated automatically:
Coarse processor structure, such as register set, pipeline, pipeline registers and test-interface.
Instruction decoder, setting control signals and data values which are carried through the pipeline and activate the respective functional units executed in context of the decoded instruction.
Pipeline controller, handling different kinds of hazards coursing pipeline interlocks, pipeline register Flushes and supporting mechanisms such as data forwarding.
Besides that, hardware operations as they are described in the LISA model can be grouped to functional units. Those functional units are synthesized as frames in case of VHDL and Verilog generation. Thus, i.e. the ports to the functional units as well as the interconnects to the pipeline registers and other functional units are automatically generated while the content needs to be filled manually with code.
If SystemC is chosen for HDL model generation the content of functional units can be additionally generated. Due to the behavior description in a LISA model is C-based the HDL generator can take full advantage of the SystemC modeling language. Therefore, the complete HDL model can be generated in SystemC.
Because of the flexibility of the LISA HDL generator the designer may concentrate onto his primary tasks and does not need to care about the error prone and long wired implementation of i.e. control path and decoder.
Case Study Results
Case studies have shown that the HDL generation from LISA is highly efficient. As well the percentage of generated VHDL code as the characteristics of the synthesized gate level model are very sufficient. In case of the ICORE architecture a DVB-T post processing unit, designed for the tasks of FFT-window-position, sampling- clock synchronization for interpolation/decimation and carrier frequency offset estimation, the following results have been reached:
The VHDL code could be generated by 82,95%. Only 17,05% of the complete model needed to be written manually.
The core size of the generated model is 666211.88 (NAND-equivalents) versus the hand written implementation of 660163,75 (NAND-equivalents).
The generated model consumes 14.51mW whereby the hand written model consumes 12,64mW.
The reason for the slightly worse numbers in power consumption of the generated model versus the handwritten is that in this study the architecture allows access to all registers and memories within the model via a test-interface. Without this unnecessary overhead, the same results as for the hand-optimized model are achievable.