Institute for Communication Technologies and Embedded Systems

GRACE - HW/SW Co-Simulation

Integration of Hardware and Software Simulators into the System Level Simulation

To increase the productivity and shorten time to market it is important to verify a heterogeneous system-on-chip (SOC) design at an early stage of the development process to prevent expensive re-designs. Here, heterogeneity is not only referring to hardware and software models but also to models specified on different abstraction levels that have to be coupled. So it is essential to have one simulation environment that understands the semantics of all models and settles the interfaces to enable communication among them. Coupling and verifying of the different parts of the target system at any time of the design process is what we call building a virtual prototype of the system as depicted in the figure below.

GRACE++ enables the integration of all specification and implementation models throughout the whole design process into a single co-simulation environment. The system specification is performed with SystemC according to our system level design methodology

For the integration of the software implementation into the virtual prototype, we employ fast LISA simulators of the programmable target architecture. LISA allows the specification of programmable architectures and the automatic generation of fast processor simulators, assemblers, linkers, compilers as well as co-simulation interfaces from an abstract machine description. The enormous speedup achieved by employing the compiled simulation technique makes the usage of cycle accurate processor models permissible. This degree of model accuracy is required when using architectures with complex pipelines keeping up simulation speed on the software side.

On the hardware side the GRACE++ co-simulation interface provides integration of various VHDL simulators to verify the hardware implementation against the abstract specification. This greatly improves the process of functional hardware verification, since tailored and realistic stimuli are generated from the system context and the writing of HDL testbenches becomes resundant. Moreover it is possible to couple physical prototypes via the RAVEN-board to the simulation environment.

System Level Design Environment for
Network-on-Chip (NoC) and
Multi-Processor platform (MP-SoC) exploration