Institute for Communication Technologies and Embedded Systems

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GRACE++ (NoC)

Design Methodology for Network-on-Chip centric Multi-Processor Platforms (MP-SoC)

Welcome to the web-pages of our SystemC based simulation environment for Network-on-Chip (NoC) centric MP-SoC platform exploration. 

Driven by the ever increasing complexity of integrated circuits, we have developed a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable System Architecture Model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. Comfortable observation and debugging capabilities of large SystemC models are provided by our graphical frontend, which displays inter process communication versus time according to the Message-Sequence-Chart notation.

The complexity and heterogeneity of current and future MP-SoC platforms require diversified on-chip communication schemes (the so-called Network on Chip design paradigm (NoC)) beyond the currently omnipresent shared bus architectures, which is inherently non-scalable. For fast iteration over the immense design space we provide a modular simulation tool that can be easily parametrized to simulate different communication topologies with the behavior of different communication technologies like e.g. AMBA, STBus or Aethereal. During the exploration cycle the framework monitors critical performance parameters and provides the designer with aggregated histogram and graph visualizations of the system bottlenecks. This enables the designer to map the inter-module traffic to an efficient communication architecture.

As joint consideration of communication and computation architecture is indispensable in future SoC designs, the system architect has to navigate through the design space spread by these parts of the system. Therefore our simulation framework also covers the spatial and temporal mapping of the functional application tasks to different processing elements. This mapping enables exploration of dedicated hardware, single threaded processors, as well as shared processing elements with Software- or Hardware Operating Systems.

To enable a seamless path from the system level domain towards the hardware and software implementation domain, the GRACE++ environment serves as an executable specification. HDL and software simulators executing the implementation models are plugged into the system level simulation via our generic co-simulation interface.

Contact

Torsten Kempf, Stefan Wallentowitz, Jens Reinecke, Andreas Wieferink, Tim Kogel, Andrea Kroll (Müllers), Guido Post, Malte Dörper, Christian Huben, Roland Nennen, Olaf Zerres

System Level Design Environment for
Network-on-Chip (NoC) and
Multi-Processor platform (MP-SoC) exploration

Publications

Kempf, T., Dörper, M., Leupers, R., Ascheid, G., Meyr, H., Kogel, T. and Vanthournout, B.: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2005
Wieferink, A., Dörper, M., Kogel, T., Braun, G., Nohl, A., Leupers, R., Ascheid, G. and Meyr, H.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms, in Computers & Digital Techniques, pp. 3-11, Jan. 2005
Wieferink, A., Dörper, M., Kogel, T., Leupers, R., Ascheid, G. and Meyr, H.: Early ISS Integration into Network-on-Chip Designs, in Int. Workshop on Systems, Architectures, Modeling and Simulation (SAMOS)(Samos (Greece)), in Int. Workshop on Systems, Architectures, Modeling and Simulation (SAMOS)(Samos (Greece)), Jul. 2004
Kogel, T. and Meyr, H.: Heterogeneous MP-SoC - The Solution to Energy-Efficient Signal Processing, in Design Automation Conference (DAC)(San Diego, USA), in Design Automation Conference (DAC)(San Diego, USA), Jun. 2004
Wieferink, A., Kogel, T., Braun, G., Nohl, A., Leupers, R., Ascheid, G. and Meyr, H.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Paris, France), Feb. 2004
Ariyamparambath, M., Bussaglia, D., Reinkemeier, B., Kogel, T. and Kempf, T.: A Highly Efficient Modeling Style for Heterogeneous Bus Architectures, in International Symposium on System-on-Chip(Tampere (Finland)), Nov. 2003
Kogel, T., Dörper, M., Wieferink, A., Leupers, R., Ascheid, G., Meyr, H. and Goossens, S.: A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks, in The First IEEE/ACM/IFIP International Conference on HW/SW Codesign and System Synthesis(Newport Beach (California USA)), Oct. 2003
Kogel, T., Wieferink, A., Leupers, R., Ascheid, G., Meyr, H., Bussaglia, D. and Ariyamparambath, M.: Virtual Architecture Mapping: A SystemC based Methodology for Architectural Exploration of System-on-Chip Designs, in Int.Workshop on Systems, Architectures, Modeling and Simulation (SAMOS)(Samos (Greece)), Jul. 2003
Kogel, T. and Bussaglia, D.: SystemC based Design of an IP Forwarding Chip with CoCentric System Studio, in Synopsys User Group Europe (SNUG)(Paris (France)), Mar. 2002
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