Institute for Communication Technologies and Embedded Systems

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GRACE - Visualization

A generic debugger enabling graphical visualization of SystemC simulation

Due to the inherent parallelism of SystemC models, text output and conventional source-code debugging are inadequate to observe and debug complex SystemC simulation models. Therefore we have developed a graphical SystemC frontend, which is specifically applicative for the visualization of abstract SystemC process networks as they occur in our System Level Design methodology.

As depicted in the snapshot above, we employ the Message Sequence Chart (MSC) principle to visualize our abstract SystemC simulation environment. Here the SystemC process instances are represented by vertical lines and the horizontal arrows are drawn in case of data exchange events. The arrows are labeled with the SystemC signal name, the time stamp of the event and the type of the exchanged token. The frontend is completely generic, i.e. all parameters like process number and names, signal names and token types are automatically configured from the current SystemC simulation.

We have implemented various filter mechanisms to reduce the complexity of the displayed process communication:

    • processes are only displayed down to a specified level in the module hierarchy
    • process instances are clickable to mask out all communication with this process
    • signals and token types are masked out by a filter dialog
    • advanced filter functionality to display only tokens with selected member values

In order to display the contents of a token, the arrows representing one token exchange are clickable and the message box depicted below occurs. Here all relevant data associated with the communication event is displayed in detail, i.e. the actual value of all token members.

Altogether our SystemC frontend provides a powerful visualization and debugging environment for complex system models with arbitrary number of process and signal instances.

Evaluation and Exploration views

To give the system architect the possibility of evaluation and exploration of his architecture and the application to architecture mapping, our framework provides quite a number of different simulation results to the system architect. Focussing on the most important these are:

Aggregated Communication graphs:

With the aggregated communication graphs the data transfers, e.g. the number of occurrencies or time consumption, between the different processing elements of the system design can be evaluated. Thus bottlenecks of the communication architecture can be easily found and resolved. An example is depicted in AggregatedGraph.jpg .

Histograms:

Additionally different histogram views for evaluation of the latencies of data transfers are generated, which enables easy exploration of congestions at the communication architectures.

Value Change Dump(VCD) traces:

VCD traces of the communication accesses are written to evaluate and verify the corresponding data transfers.