(design methodology for NoC centric Multi-Processor platforms (MP-SoC))
The GRACE++ methodology is applied in projects with our industry partners in the following application domains
Sonics Backplane III
In this research project with Sonics Inc., the GRACE++ methodology is employed to create a fast and accurate simulation model of the Sonics Backplane III communication architecture. The Sonics Backplane III is a highly complex TDMA based bus communication architecture using the Open Core Protocol (OCP) for communication.
Aethereal NoC architecture
During this research project with Philips Research Einhoven, the NoC framwork is employed to create a fast and accurate simulation model of the Aethereal On-Chip Communication architecture. The Aethereal network standard consists of a complex router topology which provides sophisticated network services to the integrated IPs.
Networking (Intel IXP2400)
To demonstrate the capabilties of our design methodology a current research project employed an IPv4 forwarding application with Quality-of-Service (QoS) functionality. On the one hand, by modeling the communication with our NoC framework a rapid analysis of the communication architecture is enabled. On the other hand, the transparent mapping of the application tasks to various shared processing elements is achieved by different Virtual Processing Element (VPU) configurations, revealing the impact on the application's performance of different processing element features like execution speed and Simultaneous Multi-Threading (SMT) support. This case study has illustrated the need of a joint consideration of functional task mapping to multi-threaded processing elements together with the on-chip communication architecture.
In this research project with Philips Research Aachen, the GRACE++ environment is employed to create a single framework for the throughout design process ofan IP switch system. First an abstract model of the switch functionality is built and successively augmented with architecture information. Hence the simulation results are aware of the architecture executing the functionality, which enables a joint optimization of algorithms and architecture. Because this is done on a high level of abstraction, changes in the functionality and the architecture can be modeled and evaluated very efficiently. In the next step the system is refined towards a synthesizable SystemC implementation and the System Studio Compiler establishes a seamless path to the hardware implementation. (more)
3D Graphic Processor
Subject of this study was the technical feasibility of the hardware implementation of a 3D ray-tracing graphic processor called Avalon. Starting point of the investigation was the software prototype and the performance specification of the ray-tracing processor. The study was jointly conducted at the chair for Integrated Systems of Signal Processing (ISS) and the chair of Electrical Engineering and Computer Systems (EECS), RWTH Aachen. In the course of this study, the GRACE++ methodology was employed to develop a generic system model for the performance evaluation of algorithmic and architectural alternatives. At EECS a physically detailed model of the VLSI implementation was created to give precise estimations on power consumption, latency and area for the dominant computational kernels. (more)