Design Automation for ASIPs

The aim of the project is to propose a methodology and implement a toolset capable to fill the beforementioned gaps, and that is flexible enough to be integrated with different existent design flows. The envisioned methodology is flexible enough to target arbitrary architectures (either completely new or inherited) while not only providing feedback related to the traditional performance metrics (speed, area, power/energy), but also enabling the designer in the algorithmic exploration process, which is a critical part of ASIP design.

Figure 2 introduces a flow diagram of the proposed methodology. On one end we receive as inputs the application specification and constraints, together with a processor model either received as an inheritance (legacy models are not uncommon) or as a first architectural devise from an experienced designer. Then, the toolset should report back to the user how well this processor model fits into the application, in the form of an accurate estimation of the achievable application performance. Such estimation process should be done quickly, based on a high level processor model. This would make design iterations very fast, as it eliminates the need for actual architecture implementation, synthesis and simulation. This resulting model is going to be the entry point for and existing ADL-Based flow.

Performance Estimation for Tailored Datapaths and Instruction Sets

One of the first design steps of ASIP design consists on envisioning an instruction set (and the underlying datapath) that properly matches an application. To do this in a time efficient manner, we have proposed and implemented an engine that can accurately estimate the application performance (in clock cycles) of an envisioned architecture given by the designer. The estimation process starts with the application source code (C) and a high level processor model provided by the designer. Then, the application is compiled into a compiler intermediate representation and its costs are calculated according to the processor model. These costs are then merged with profile information in order to derive a performance figure in clock cycles. Our engine supports the following use cases, as shown in Figure 3.

• Instruction Set and Datapath Design
• Custom Hardware block integration
• Evaluation of what-if customization scenarios

We have evaluated our performance estimation engine mainly focused on two goals. The first one was to provide a comprehensive validation of the estimates by extracting cycle accurate simulation results from well-known benchmarks executed in commercially available processors, such as:

• Synopsys Processor Designer RISC (PD-RISC)
• Texas Instruments C64x, C66x and C67x  DSPs

From Figure 4, we can observe that we are able to obtain estimates that are in average within 15% of the actual simulation results, while being able to provide the estimates much faster than using simulators. In average we have a gain of 248x over the PD-RISC simulators and of 67x over the TI simulators. The second approach was to use the engine during an ASIP design case study, and validate the results obtained during the estimations with those obtained from actual architectural simulation (cycle-accurate). During these process we could observe that the estimation errors were similar to those observed during the initial validation. For more detailed results and analyses, please refer to the listed publications.