SHAPES is an EU project which aims at building an embedded massive parallel processing system. There is no processing power ceiling for the demand of low consumption, low cost, dense DSP for future embedded audio, video, human-centric applications. Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. The main problem is wiring, which threats Moore's law. Future computing architectures for Embedded DSP and Control are strategic and deserve adequate research efforts. Tiled architectures suggest a possible HW path: "small" processing tiles connected by "short wires".
Tiled Architectures will cover a significant share of 10+ year embedded applications. SHAPES will set a new density record with multi-Teraops single-board computers and multi-Petaops systems, and will be based on a groundbreaking HW/SW architecture paradigm. The heterogeneous SHAPES tile is composed of a VLIW floating-point DSP, a RISC, on chip memory, and a network interface. It includes a few million gates, for optimal balance among parallelism, local memory, and IP reuse on future technologies. The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbor's toroidal engineering methodologies will be used for off-chip networking and maximum system density.