Institute for Communication Technologies and Embedded Systems

CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design

Eusse, J. F. ,  Williams, C. ,  Leupers, R.
Book Title:
International Workshop on Reconfigurable Communication-centric Systems-on-Chip
Jul. 2013
Application Specific Instruction Set Processor (ASIP) design methodologies have not been significantly altered during the past decade, and are still based on a highly manual and iterative process. Profiling has been established as a first step to prune the design space, and gain a deep understanding of the algorithms that underpin the application for which an ASIP is to be tailored. Independently of the profiling strategy, none of the existing ASIP-oriented profiling technologies enables on-the-loop application optimization or algorithmic exploration, which are mandatory steps throughout ASIP design. An innovative multi-grained approach that enables multiple levels of profiling detail according to the ASIP design stage (i.e. hot spot identification, application optimization, algorithmic exploration and architectural design) is presented. To validate our multi-grained profiling approach, the design of an ASIP for Marker-Based Augmented Reality was undertaken, achieving a 6x speedup in application execution in two days of design time.