Institute for Communication Technologies and Embedded Systems: Alumni Assistant: Jan Henrik Weinstock

Sie verwenden einen Browser, in dem JavaScript deaktiviert ist. Dadurch wird verhindert, dass Sie die volle Funktionalität dieser Webseite nutzen können. Zur Navigation müssen Sie daher die Sitemap nutzen.

You are currently using a browser with deactivated JavaScript. There you can't use all the features of this website. In order to navigate the site, please use the Sitemap .

Publications

Publications from Jun/ 2024 to 2013

Bosbach, N., Zurstraßen, N., Pelke, R., Jünger, L., Weinstock, J. H. and Leupers, R.: Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models, in Design Automation Conference , Jun. 2024, accepted for publication, 10.1145/3649329.3658257
Bosbach, N., Pelke, R., Zurstraßen, N., Jünger, L., Weinstock, J. H. and Leupers, R.: Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TLM-2.0-based Virtual Platforms, in International Conference on Hardware/Software Codesign and System Synthesis , Sep. 2023, 10.1145/3607888.3608596
Zurstraßen, N., Bosbach, N., Joseph, J. M., Jünger, L., Weinstock, J. H. and Leupers, R.: Efficient RISC-V-on-x64 Floating Point Simulation, in ICCD, 2023, 10.1109/ICCD58817.2023.00090 ©2023 IEEE
Buecs, R., Pramod, L., Weinstock, J. H., Walbroel, F., Leupers, R. and Ascheid, G.: A Multi-Domain Co-Simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping, in Smart Cities, Green Technologies, and Intelligent Transport Systems: 4th International Conference, SMARTGREENS 2015, and 1st International Conference VEHITS 2018, Revised Selected Papers, Vol. 992, Springer, pp. 181-201, Mar. 2019, 10.1007/978-3-030-26633-2_9
Jünger, L., Weinstock, J. H., Leupers, R. and Ascheid, G.: Fast SystemC Processor Models with Unicorn, in Proceedings of the 2019 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan. 2019, 10.1145/3300189.3300191
Weinstock, J. H., Buecs, R., Walbroel, F., Leupers, R. and Ascheid, G.: AMVP - a high performance virtual platform using parallel SystemC for multicore ARM architectures: work-in-progress, in International Conference on Hardware/Software Codesign and System Synthesis (CODES) (Piscataway, NJ, USA), pp. 13:1--13:2, IEEE Press, Sep. 2018, ISBN: 978-1-53865-562-7
Weinstock, J. H.: Parallel SystemC Simulation for Electronic System Level Design, Ph. D. Dissertation RWTH Aachen University, Jun. 2018, 10.18154/RWTH-2018-225554
Buecs, R., Pramod, L., Weinstock, J. H., Walbroel, F., Leupers, R. and Ascheid, G.: Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem, in Proceedings of the 4th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) 2018, pp. 59-69, Mar. 2018, 10.5220/0006665900590069
Weinstock, J. H., Leupers, R. and Ascheid, G.: Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models, in Proceedings of the 2017 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools(Stockholm, Sweden), Jan. 2017, ISBN: 978-1-45034-840-9, 10.1145/3023973.3023975
Weinstock, J. H., Murillo, L. G., Leupers, R. and Ascheid, G.: Parallel SystemC Simulation for ESL Design, in (ACM TECS), Vol. 16, No. 1, ACM, pp. 27:1--27:25, Oct. 2016, ISSN: 1539-9087, 10.1145/2987374
Marcu, M., Boncalo, O., Weinstock, J. H. and Leupers, R.: Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting, in ARCS 2016 - Architecture of Computing Systems(Nuremberg, Germany), Apr. 2016, 10.1007/978-3-319-30695-7_21
Weinstock, J. H., Leupers, R., Ascheid, G., Petras, D. and Hoffmann, A.: SystemC-Link: Parallel SystemC Simulation using Time-Decoupled Segments, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Dresden, Germany), Mar. 2016
Weinstock, J. H., Leupers, R. and Ascheid, G.: Parallel SystemC Simulation for ESL Design using Flexible Time Decoupling, in Proceedings of the Workshop on Virtual Prototyping of Parallel and Embedded Systems (VIPES 2015)(Samos, Greece), pp. 378 - 383, Jul. 2015, ISBN: 978-1-46737-311-1, 10.1109/SAMOS.2015.7363702 ©2015 IEEE
Weinstock, J. H., Leupers, R. and Ascheid, G.: Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator, in Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2015)(St. Goar, Germany), Jun. 2015
Cosmin, C.-G., Marcu, M., Wang, Z., Chattopadhyay, A., Amaricai, A., Fedeac, S., Ghenea, M., Weinstock, J. H. and Leupers, R.: Direct FPGA-based Power Profiling for a RISC Processor, in IEEE International Instrumentation and Measurement Technology Conference (I2MTC)(Pisa, Italy), pp. 1578 - 1583 , May. 2015, 10.1109/I2MTC.2015.7151514 ©2015 IEEE
Paolucci, P. S., Biagioni, A., Murillo, L. G., Rousseau, F., Schor, L., Tosoratto, L., Bacivarov, I., Buecs, R., Deschamps, C., El Antably, A., Ammendola, R., Fournel, N., Frezza, O., Leupers, R., Lo Cicero, F., Lonardo, A., Martinelli, M., Pastorelli, E., Rai, D., Rossetti, D., Simula, F., Thiele, L., Vicini, P. and Weinstock, J. H.: Dynamic Many-process Applications on Many-tile Embedded Systems and HPC Clusters: the EURETILE programming environment and execution platforms, in Elsevier Journal of Systems Architecture, 2015, 10.1016/j.sysarc.2015.11.008
Schumacher, C., Weinstock, J. H., Leupers, R., Ascheid, G., Tosoratto, L., Lonardo, A., Petras, D. and Hoffmann, A.: legaSCi: Legacy SystemC Model Integration into Parallel Simulators, in (ACM TECS), Vol. 13, No. 5s, ACM, pp. 165:1--165:24, Dec. 2014, ISSN: 1539-9087, 10.1145/2678018
Schor, L., Bacivarov, I., Murillo, L. G., Paolucci, P. S., Rousseau, F., El Antably, A., Buecs, R., Fournel, N., Leupers, R., Rai, D., Thiele, L., Tosoratto, L., Vicini, P. and Weinstock, J. H.: EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications onto Many-Tile Systems, in IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)(Milan, Italy), Aug. 2014, 10.1109/ISPA.2014.32 ©2014 IEEE
Weinstock, J. H., Schumacher, C., Leupers, R., Ascheid, G. and Tosoratto, L.: Time-Decoupled Parallel SystemC Simulation, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), European Design and Automation Association, 2014, 10.7873/DATE.2014.204 ©2014 IEEE
Weinstock, J. H., Schumacher, C., Leupers, R. and Ascheid, G.: SCandal: SystemC Analysis for Nondeterminism Anomalies, in Models, Methods, and Tools for Complex Chip Design,Vol. 265, 2013