Institute for Communication Technologies and Embedded Systems

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications onto Many-Tile Systems

Schor, L. ,  Bacivarov, I. ,  Murillo, L. G. ,  Paolucci, P. S. ,  Rousseau, F. ,  El Antably, A. ,  Buecs, R. ,  Fournel, N. ,  Leupers, R. ,  Rai, D. ,  Thiele, L. ,  Tosoratto, L. ,  Vicini, P. ,  Weinstock, J. H.
Book Title:
IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)
Milan, Italy
Aug. 2014
EURETILE investigates foundational innovations in the design of massively parallel tiled computing systems by introducing a novel parallel programming paradigm and a multi-tile hardware architecture. Each tile includes multiple general-purpose processors, specialized accelerators, and a fault-tolerant distributed network processor, which connects the tile to the inter-tile communication network. This paper focuses on the EURETILE software design flow, which provides a novel programming environment to map multiple dynamic applications onto a many-tile architecture. The elaborated high-level programming model specifies each application as a network of autonomous processes, enabling the automatic generation and optimization of the architecture-specific implementation. Behavioral and architectural dynamism is handled by a hierarchically organized runtime-manager running on top of a lightweight operating system. To evaluate, debug, and profile the generated binaries, a scalable many-tile simulator has been developed. High system dependability is achieved by combining hardware-based fault awareness strategies with software-based fault reactivity strategies. We demonstrate the capability of the design flow to exploit the parallelism of many-tile architectures with various embedded and high performance computing benchmarks targeting the virtual EURETILE platform with up to 192 tiles.