Technical achievements in the last decade had awoken everyone’s desire of possessing powerful mobile devices to be connected to everyone everywhere. The resulting ever increasing computational workload combined with tighter power budgets – due to heat issues and battery lifetime – enforces new design decisions for hardware and software. Heterogeneous multi- and many-processor systems on chip (MPSoC) composed of different core architectures are seen as solution exploiting the advantages of MPSoCs. However, one of the biggest hurdles to exploit multicore architectures from the software side is how to efficiently develop performance and power co-optimised parallel software. Making the right decisions in the vast SW design space can hardly be done by the programmer in a reasonable time frame, especially, when performing a manual design process. Considering an application that has been properly partitioned into multiple concurrent tasks, and programmed in a parallel language, the process of mapping those tasks onto the processors with the optimal voltage and frequency setting is a huge challenge for a certain design goal. Moreover, previous research on the problem has proven this as being NP-hard. Therefore, an automatic approach is needed that determines the optimal decision, given an optimisation constraint. A great amount of research has been conducted at ICE aiming to optimise the performance of a parallelised application. See MAPS. The Silexica GmbH, a VC-backed spin-off from ICE, continues on this track of producing novel compiler technology and tools for programming embedded multicore platforms, and offers the tools and knowledge to the industry.
In order to co-optimise for power and performance, accurate power modelling and new algorithms have to be developed and integrated into the existing performance driven framework. ICE’s electronic system-level (ESL) power estimation methodology for processor, on-chip interconnect, and other SoC components is a more than consequent starting point to deploy power models for the power-aware mapping environment. Find out more about the ESL power estimation methodology here.
Based on the power modelling capability, the mapper tool flow (Figure 1) is extended with a novel power-aware software mapping heuristic which has been implemented to develop performance and power co-optimized parallel software. This algorithm is verified in several case studies and used to identify the gain of sophisticated power management techniques by providing the power-performance trade-off (Figure 2).