HySim: Hybrid Simulation Framework

Processor and SoC Simulation

Introduction

Fast and accurate simulation of MPSoC systems is a key factor for both embedded software development and design space exploration. The growing complexity of today's heterogeneous MPSoCs poses new challenges that are difficult to handle with current simulation techniques. In terms of simulation, complexity refers mainly to amount of Programmable Processing Elements (PPE) running in parallel, among others. Our Hybrid Processor Simulation approach -HySim- provides mechanisms to speed-up simulation by increasing the abstraction level of simulated PPEs when possible, while the accuracy-speed trade-off is still under the user control.

 

    Contributions

    HySim was conceived to support real-life MPSoC design scenarios from the beginning. Therefore, its main contribution is the possibility to handle and exploit the accuracy-speed trade-off depending on the developer's demand. Fast Abstract Simulation can be chosen to reach any state of the system under simulation when developer looks for speed and consistent behavior (e.g. for software development and debugging). Accurate Target Simulation can be chosen when developer is interested in fine grain details (e.g. system verification, timing validation).
     

      HySim Overview

      A processor simulator using HySim consists of an Instruction Set Simulator, named as Target Simulator (TS), and an Abstract Simulator (AS). The AS is a virtual machine for the C programming language, which provides fast native execution for time-consuming functions, when the function source code is available. TS and AS are exposed together as a unified processor simulator to the simulation kernel, but internally execution control is transparently switched at runtime.

      The hybridization facilitates to exploit the trade-off between simulation speed and accuracy on user demand. Performance profiling/optimization, can be performed on particular parts of the application, whereas other parts can be accelerated while keeping only its functionality. In these terms, the whole application will be functionally verified, while accurate timing information will be gathered only when required.

      Quick performance estimation, without TS execution, is also possible by using AS as the execution engine. Currently there are two approaches (performance annotation and dynamic profiling) developed for RISC like processors or DSP/VLIW architectures respectively.

      All these features (dynamic execution engine switching, performance annotation and dynamic profiling) are supported by an extensible instrumenter, which transforms the C source code of the application. The transformed code does not behave normally anymore, but it also imitates the behavior that a third-party target compiler would introduce in the target binary. For this reason the transformation is also called virtualization. The transformed code is compiled by the native compiler, and the generated binary can be executed by the AS, which can be customized to perform cache simulation and dynamic profiling. The Hybrid Simulation workflow is presented in the figure shown below.

        Performance estimation and timing annotation are essential parts of the virtualization chain. Dynamic profiling, Cross-replay and statistical methods have been researched and used in the context of the HySim project. Support of extensible processor architectures and adequate methods for temporal synchronization, particularly when in a full-system simulation environment, have been covered within this project as well.

        Contact

        Luis Gabriel Murillo, Jovana Jovic, Stefan Boßung (Kraemer), Lei Gao, Sergey Yakoushkin

        Publications

        Stulova, A., Leupers, R. and Ascheid, G.: Throughput Driven Transformations of Synchronous Data Flows for Mapping to Heterogeneous MPSoCs, in SAMOS XII: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Jul. 2012, ISBN: 978-1-46732-296-6 ©2012 IEEE


        Willems, M., Warmers, M. and Zivojnovic, V.: DSP-Compiler: auf dem Weg zum Produktionstool ?, in Design & Elektronik, No. 24/25, pp. 47-48, Dec. 1995


        Ceng, J.: A Methodology for Efficient Multiprocessor System-on-Chip Software Development, Ph. D. Dissertation RWTH Aachen Univeristy, 2011 ©2011 IEEE


        Gao, L., Kraemer, S., Karuri, K., Leupers, R., Ascheid, G. and Meyr, H.: An Integrated Performance Estimation Approach in a Hybrid Simulation Framework, in MoBS (Beijing, China), in MoBS (Beijing, China), Jun. 2008


        Godtmann, S., Ispas, A. and Ascheid, G.: Convergence Analysis of Code-Aided Channel Estimation by Means of Transfer Charts, in Proc. Int. Symp. on Turbo Codes and Related Topics(Lausanne, Switzerland), Sep. 2008, 10.1109/TURBOCODING.2008.4658719 ©2008 IEEE


        Gao, L., Kraemer, S., Leupers, R., Ascheid, G. and Meyr, H.: A Fast and Generic Hybrid Simulation Approach using C Virtual Machine, in Proceedings of the Conference on Compilers, Architecture, and Synthesis For Embedded Systems (CASES '07)(Salzburg, Austria), in Proceedings of the Conference on Compilers, Architecture, and Synthesis For Embedded Systems (CASES '07)(Salzburg, Austria), Oct. 2007


        Kogel, T., Dörper, M., Kempf, T., Wieferink, A., Leupers, R., Ascheid, G. and Meyr, H.: Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs, in SAMOS, in SAMOS, pp. 138-148, 2004