Digital system design is characterized by ever increasing system complexity that has to be implemented within reduced time, resulting in minimum costs and especially a short time-to-market. These characteristics call for a seamless design flow that allows to perform the suitable design steps on the highest level of abstraction.
Fixed-point implementations are preferred to floating-point implementations whenever the system is sensitive to power consumption, execution speed, chip size and device prices. On the other hand, fixed-point system design requires a specific design flow, which up to now is time consuming and error prone. This design flow is illustrated by the following diagram.
Algorithm design starts from a floating-point description. This allows to ignore the effects of finite word lengths and fixed exponents and to abstract from all implementation details. The algorithm space can be evaluated in the most efficient way, only concentrating on whether the algorithm fulfills the performance requirements of the system, such as bit error rate or speech quality. The abstraction allows a maximum of design reuse. The floating-point description can be done using a block diagram description (which up to now is very much limited to dataflow oriented applications), where the functional blocks can be user defined (using a high level language) or come from a library. As well, a high level language such as 'C' can be used for the floating-point description of the algorithm. Most of the block diagram descriptions can be automatically translated into a high level language description.
On the fixed-point level, to all operands a fixed word length and a fixed exponent is assigned, while the control structure and the operations of the floating point program remain unchanged. This description is used to analyze whether the fixed-point model fulfills the algorithmic system requirements.
The transformation from the floating-point level to the fixed-point level is not unique but a complex design space exists. Design criterion is a performance true transformation, expressing that the fixed-point specification fulfills the system requirements. Especially for HW and SW implementations, different fixed-point specifications might be preferable, so that for a typical design (and especially in HW/SW codesign) multiple transformations from the floating-point level to the fixed-point level are necessary to result in a near optimum solution.
So far, this transformation has to be done manually. This is an error prone and time consuming process even for a single transformation. For more complex applications this takes more than 50% of the design time once the floating-point algorithm is fixed. Keeping increasing system complexities and time-to-market pressure in mind, there is a strong demand for an automated transformation. On the implementational level, the fixed-point model of the algorithm has to be transferred into the best suited target description, either using a hardware description language (HDL) or a programming language. These transformations are not unique but address a large design space.
