Publications of Prof. Gerd Ascheid

Publications of Prof. Gerd Ascheid

Publications from Mar/ 2020 to Oct/ 2018

Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs, in ARCS - International Conference on Architecture of Computing Systems, Mar. 2020, accepted for publication


Schlupkothen, S., Heidenblut, T. and Ascheid, G.: Random field-aided tracking of autonomous kinetically passive wireless agents, in {EURASIP} Journal on Advances in Signal Processing, Vol. 2020, No. 1, Springer Science and Business Media {LLC}, Feb. 2020, 10.1186/s13634-019-0657-x


Copic, M., Leupers, R. and Ascheid, G.: Reducing Idle Time in Event-Triggered Software Execution via Runnable Migration and DPM-Aware Scheduling, in Integration, the VLSI Journal, Vol. 70, Elsevier, pp. 10-20, Jan. 2020, 10.1016/j.vlsi.2019.09.004


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA, in (Integration), Vol. 69, Elsevier, pp. 50-61, Nov. 2019, 10.1016/j.vlsi.2019.09.005


Schlupkothen, S. and Ascheid, G.: Multiple particle filtering for tracking wireless agents via Monte Carlo likelihood approximation, in {EURASIP} Journal on Advances in Signal Processing, Vol. 2019, No. 1, Springer Science and Business Media {LLC}, Nov. 2019, 10.1186/s13634-019-0643-3


Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Vol. 11, No. 3, pp. 93-96, Sep. 2019, 10.1109/LES.2019.2901224 ©2019 IEEE


Topal, O. A., Demir, , Dartmann, G., Schmeink, A., Ascheid, G., Pusane, A. E. and Karabulut Kurt, G.: Physical Layer Spoofing Against Eavesdropping Attacks, in The 8th Mediterranean Conference on Embedded Computing - MECO'2019 , pp. 1-5, Jun. 2019, ISSN: 2377-5475, 10.1109/MECO.2019.8760168 ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 2019 IEEE European Test Symposium (ETS), pp. 1-6, May. 2019, ISSN: 1530-1877, 10.1109/ETS.2019.8791528 ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE


Bytyn, A., Leupers, R. and Ascheid, G.: An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May. 2019, ISBN: 978-1-72810-397-6, 10.1109/ISCAS.2019.8702357


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), IEEE, p. 4, Apr. 2019, 10.1109/VLSI-DAT.2019.8741531 ©2019 IEEE


Buecs, R., Pramod, L., Weinstock, J. H., Walbroel, F., Leupers, R. and Ascheid, G.: A Multi-Domain Co-Simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping, in Smart Cities, Green Technologies, and Intelligent Transport Systems: 4th International Conference, SMARTGREENS 2015, and 1st International Conference VEHITS 2018, Revised Selected Papers, Vol. 992, Springer, pp. 181-201, Mar. 2019, 10.1007/978-3-030-26633-2_9


Birke, S., Auras, D., Piwczyk, T., Mahlke, R., Alberti, N., Leupers, R. and Ascheid, G.: VLSI Architectures for ORVD Trellis based MIMO Detection, in 2019 International Conference on Computing, Networking and Communications (ICNC), Feb. 2019, 10.1109/ICCNC.2019.8685585 ©2019 IEEE


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Shaheen, A.: A Heuristic for Multi Objective Software Application Mappings on Heterogeneous MPSoCs, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2019, 10.1145/3287624.3287651


Copic, M., Leupers, R. and Ascheid, G.: Efficient Sporadic Task Handling in Parallel AUTOSAR Applications Using Runnable Migration, in Proceedings of the 24th Asia and South Pacific Design Automation Conference(New York, NY, USA), pp. 603-608 , ACM, Jan. 2019, ISBN: 978-1-45036-007-4, 10.1145/3287624.3287654


Jünger, L., Weinstock, J. H., Leupers, R. and Ascheid, G.: Fast SystemC Processor Models with Unicorn, in Proceedings of the 2019 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan. 2019, 10.1145/3300189.3300191


Hallawa, A., Zechendorf, E., Song, Y., Schmeink, A., Peine, A., Marin, L., Ascheid, G. and Dartmann, G.: On the Use of Evolutionary Computation for In-Silico Medicine: Modelling Sepsis via Evolving Continuous Petri Nets, in Evostar Conference(Cham), pp. 254--269, Springer International Publishing, 2019, ISBN: 978-3-03016-692-2, 10.1007/978-3-030-16692-2_17


Tedik, S., Karabulut Kurt, G., Oke, G., Schmeink, A., Ascheid, G. and Dartmann, G.: The Safety Analysis: Disagreement of Wireless Communication-based Consensus, in IEEE Wireless Communication Letters, Vol. 7, No. 6, pp. 998-1001, Dec. 2018, ISSN: 2162-2345, 10.1109/LWC.2018.2844162


Schlupkothen, S. and Ascheid, G.: Particle Filter Based Tracking of Highly Agile Wireless Agents via Random Input Sampling, in 2018 6th IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE) (WiSEE 2018)(Huntsville, USA), pp. 227-232, Dec. 2018, ISSN: 2380-7628, 10.1109/WiSEE.2018.8637343


Buecs, R., Leupers, R. and Ascheid, G.: Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping, in 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 532-535, IEEE, Oct. 2018, 10.1109/APCCAS.2018.8605685 ©2018 IEEE


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