Publications from Oct/ 2022 to Apr/ 2019

• Birke, S., Hartmann, B., Auras, D., Wloka, M., Ascheid, G. and Leupers, R.: Design and Exploration of an ARC-Coprocessor for LSTM Based Audio Applications, in 2022 IEEE Nordic Circuits and Systems Conference (NorCAS) , Oct. 2022, 10.1109/NorCAS57515.2022.9934553 ©2022 IEEE
  
• Birke, S., Hartmann, B., Auras, D., Wloka, M., Ascheid, G. and Leupers, R.: Design and Exploration of an ARC-Coprocessor for LSTM Based Audio Applications, in 2022 IEEE Nordic Circuits and Systems Conference (NorCAS), pp. 1-7, 2022, 10.1109/NorCAS57515.2022.9934553 ©2022 IEEE
  
• Liang, Z. and Ascheid, G.: Subcarrier Grouping with Linear Time-Domain Compensation for Low-Complexity Millimeter Wave OFDM Multiuser Systems, in Proceedings of IEEE Vehicular Technology Conference (VTC-Fall), pp. 1-5, IEEE, Sep. 2021, 10.1109/VTC2021-Fall52928.2021.9625504 ©2021 IEEE
  
• Copic, M., Leupers, R. and Ascheid, G.: Leveraging Nondeterminism in Mixed Classic/Adaptive AUTOSAR Systems for Runnable Configuration, in Design Automation Conference (DAC), Work-in-Progress Session, 2021, accepted for publication
  
• Copic, M., Leupers, R. and Ascheid, G.: Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism, in Proceedings of 24th Euromicro Conference on Digital System Design (DSD), 2021, 10.1109/DSD53832.2021.00070
  
• Bytyn, A., Leupers, R. and Ascheid, G.: ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNN, in IEEE Open Journal of Circuits and Systems, Vol. 2, pp. 3-15, 2021, 10.1109/OJCAS.2020.3037758
  
• Liang, Z., Wu, S.-j. and Ascheid, G.: Low Time-Complexity Learning-Aided Codebook-Based Beam Forming Selection in MmWave System, in Proceedings of European Wireless Conference (EW), VDE, 2021, ISBN: 978-3-80075-672-8
  
• Copic, M., Leupers, R. and Ascheid, G.: Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables, in Proceedings of 31st International Symposium on Software Reliability Engineering (ISSRE), pp. 127-137, Oct. 2020, 10.1109/ISSRE5003.2020.00021 ©2020 IEEE
  
• Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs, in ARCS - International Conference on Architecture of Computing Systems, Mar. 2020, ISBN: 978-3-03052-794-5, 10.1007/978-3-030-52794-5_5
  
• Schlupkothen, S., Heidenblut, T. and Ascheid, G.: Random field-aided tracking of autonomous kinetically passive wireless agents, in {EURASIP} Journal on Advances in Signal Processing, Vol. 2020, No. 1, Springer Science and Business Media {LLC}, Feb. 2020, 10.1186/s13634-019-0657-x
  
• Copic, M., Leupers, R. and Ascheid, G.: Reducing Idle Time in Event-Triggered Software Execution via Runnable Migration and DPM-Aware Scheduling, in Integration, the VLSI Journal, Vol. 70, Elsevier, pp. 10-20, Jan. 2020, 10.1016/j.vlsi.2019.09.004
  
• Topal, O. A., Demir, , Liang, Z., Pusane, A. E., Dartmann, G., Ascheid, G. and Kur, G. K.: A Physical Layer Security Framework for Cognitive Cyber-Physical Systems, in IEEE Wireless Communications, Vol. 27, No. 4, pp. 32-39, 2020, 10.1109/MWC.01.1900543
  
• Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA, in (Integration), Vol. 69, Elsevier, pp. 50-61, Nov. 2019, 10.1016/j.vlsi.2019.09.005
  
• Schlupkothen, S. and Ascheid, G.: Multiple particle filtering for tracking wireless agents via Monte Carlo likelihood approximation, in {EURASIP} Journal on Advances in Signal Processing, Vol. 2019, No. 1, Springer Science and Business Media {LLC}, Nov. 2019, 10.1186/s13634-019-0643-3
  
• Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Vol. 11, No. 3, pp. 93-96, Sep. 2019, 10.1109/LES.2019.2901224 ©2019 IEEE
  
• Topal, O. A., Demir, , Dartmann, G., Schmeink, A., Ascheid, G., Pusane, A. E. and Karabulut Kurt, G.: Physical Layer Spoofing Against Eavesdropping Attacks, in The 8th Mediterranean Conference on Embedded Computing - MECO'2019 , pp. 1-5, Jun. 2019, ISSN: 2377-5475, 10.1109/MECO.2019.8760168 ©2019 IEEE
  
• Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 2019 IEEE European Test Symposium (ETS), pp. 1-6, May. 2019, ISSN: 1530-1877, 10.1109/ETS.2019.8791528 ©2019 IEEE
  
• Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE
  
• Bytyn, A., Leupers, R. and Ascheid, G.: An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS) , IEEE, May. 2019, ISBN: 978-1-72810-397-6, 10.1109/ISCAS.2019.8702357
  
• Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), IEEE, p. 4, Apr. 2019, 10.1109/VLSI-DAT.2019.8741531 ©2019 IEEE
  

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