Publications of Prof. Gerd Ascheid

Publications of Prof. Gerd Ascheid

Publications from May/ 2019 to Mar/ 2018

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 24th IEEE European Test Symposium (ETS'19), May. 2019, accepted for publication ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE


Bytyn, A., Leupers, R. and Ascheid, G.: An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May. 2019, ISBN: 978-1-72810-397-6, 10.1109/ISCAS.2019.8702357


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2019


Birke, S., Auras, D., Piwczyk, T., Mahlke, R., Alberti, N., Leupers, R. and Ascheid, G.: VLSI Architectures for ORVD Trellis based MIMO Detection, in 2019 International Conference on Computing, Networking and Communications (ICNC), Feb. 2019, 10.1109/ICCNC.2019.8685585 ©2019 IEEE


Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Feb. 2019, accepted for publication, 10.1109/LES.2019.2901224


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Shaheen, A.: A Heuristic for Multi Objective Software Application Mappings on Heterogeneous MPSoCs, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2019, 10.1145/3287624.3287651


Copic, M., Leupers, R. and Ascheid, G.: Efficient Sporadic Task Handling in Parallel AUTOSAR Applications Using Runnable Migration, in 24th Asia and South Pacific Design Automation Conference (ASP-DAC 2019), Jan. 2019, accepted for publication


Jünger, L., Weinstock, J. H., Leupers, R. and Ascheid, G.: Fast SystemC Processor Models with Unicorn, in Proceedings of the 2019 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan. 2019, 10.1145/3300189.3300191


Buecs, R., Pramod, L., Weinstock, J. H., Walbroel, F., Leupers, R. and Ascheid, G.: A Multi-Domain Co-Simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping, in Smart Cities, Green Technologies, and Intelligent Transport Systems: 4th International Conference, SMARTGREENS 2015, and 1st International Conference VEHITS 2018, Revised Selected Papers, 2019, accepted for publication


Hallawa, A., Zechendorf, E., Song, Y., Schmeink, A., Peine, A., Marin, L., Ascheid, G. and Dartmann, G.: On the Use of Evolutionary Computation for In-Silico Medicine: Modelling Sepsis via Evolving Continuous Petri Nets, in Evostar Conference, 2019, accepted for publication


Schlupkothen, S. and Ascheid, G.: Particle Filter Based Tracking of Highly Agile Wireless Agents via Random Input Sampling, in 2018 6th IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE) (WiSEE 2018)(Huntsville, USA), Dec. 2018, accepted for publication


Buecs, R., Leupers, R. and Ascheid, G.: Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping, in 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2018 ©2018 IEEE


Buecs, R., Marcel, H., Leupers, R. and Ascheid, G.: Multi-Scale Code Generation for Simulation-Driven Rapid ADAS Prototyping: the SMELT Approach, in 2018 IEEE International Conference on Vehicular Electronics and Safety (ICVES), Sep. 2018, 10.1109/ICVES.2018.8519593 ©2018 IEEE


Weinstock, J. H., Buecs, R., Walbroel, F., Leupers, R. and Ascheid, G.: AMVP - a high performance virtual platform using parallel SystemC for multicore ARM architectures: work-in-progress, in International Conference on Hardware/Software Codesign and System Synthesis (CODES)(Piscataway, NJ, USA), pp. 13:1--13:2, IEEE Press, Sep. 2018, ISBN: 978-1-53865-562-7


Andraud, M., Hallawa, A., De Roose, J., Cantatore, E. , Ascheid, G. and Verhelst, M.: Evolving Hardware Online Instinctive Behaviors in Resource-scarce Agent Swarms Exploring Hard-to-reach Environments, in Proceedings of the Genetic and Evolutionary Computation Conference Companion(New York, NY, USA), ACM, Jul. 2018, ISBN: 978-1-45035-764-7, 10.1145/3205651.3208255


Šišejković, D., Leupers, R., Ascheid, G. and Metzner, S.: A Unifying Logic Encryption Security Metric, in International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul. 2018, 10.1145/3229631.3229636


Schlupkothen, S. and Ascheid, G.: Localization of ambiguously identifiable wireless agents: complexity analysis and efficient algorithms, in (EURASIP ASP), Vol. 2018, No. 1, p. 30, May. 2018, ISSN: 1687-6180, 10.1186/s13634-018-0548-6


Laux, H., Bytyn, A., Ascheid, G., Schmeink, A., Karabulut Kurt, G. and Dartmann, G.: Learning-Based Indoor Localization for Industrial Applications, in Workshop on Sensor Data Fusion and Machine Learning for next Generation of Cyber-Physical-Systems in conjunction with ACM International Conference on Computing Frontiers 2018, pp. 355-362 , ACM New York, NY, May. 2018, 10.1145/3203217.3203227


Schlupkothen, S., Hallawa, A. and Ascheid, G.: Evolutionary Algorithm Optimized Centralized Offline Localization and Mapping, in 2018 International Conference on Computing, Networking and Communications (ICNC), Mar. 2018, 10.1109/ICCNC.2018.8390410 ©2018 IEEE


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