Modern embedded system designs include complex multi-core processors, multi-level memory hierarchies and specialized hardware accelerators for radio or image processing. Each single component has to be simulated individually, causing simulation performance to drop.
Traditional techniques attempt to counter this by raising the abstraction level of the simulation models. A typical example of this is Transaction Level Modeling (TLM), where communication between components is abstracted by passing messages (transactions) using interface method calls (IMCs) instead of modeling individual signals.
An orthogonal approach to TLM is to distribute the simulation work among multiple cores on the host system. Today's multi-core workstations are equipped with multiple processing cores, making them an ideal target for parallel simulation. However, traditional simulation engines such as the OSCI SystemC kernel only use a single thread for simulation, thereby leaving a lot of computational potential unused.