Parallel SystemC Simulation

Modern embedded system designs include complex multi-core processors, multi-level memory hierarchies and specialized hardware accelerators for radio or image processing. Each single component has to be simulated individually, causing simulation performance to drop.

Traditional techniques attempt to counter this by raising the abstraction level of the simulation models. A typical example of this is Transaction Level Modeling (TLM), where communication between components is abstracted by passing messages (transactions) using interface method calls (IMCs) instead of modeling individual signals.

An orthogonal approach to TLM is to distribute the simulation work among multiple cores on the host system. Today's multi-core workstations are equipped with multiple processing cores, making them an ideal target for parallel simulation. However, traditional simulation engines such as the OSCI SystemC kernel only use a single thread for simulation, thereby leaving a lot of computational potential unused.

The SCope SystemC kernel is a custom simulation kernel and fully compatible with the IEEE SystemC standard. It deploys time-decoupling to distribute simulation load over multiple host cores. Each simulation thread has its own state, such as time, and executes its own simulation loop in a decoupled fashion: the local time-stamps of the individual threads are allowed to deviate from each other up to a constant defined as the lookahead. This decoupling allows for a much better performance, since threads need not wait for another as long as they stay within the lookahead interval. However, this increased parallel performance comes at a price: all communication between threads (e.g. TLM transactions) needs to be stated sufficiently ahead of time to ensure, that the supposed arrival time-stamp of the message has not yet elapsed in the context of the target thread. This is due to the fact that the exact time-stamp on the receiver side is not known exactly, only that it must lie within the lookahead interval. Sometimes, however, designers cannot state transactions ahead of time. SCope deals with this problem by imposing an artificial delay on the transaction before transmission. This incurs a timing error for the transaction, but allows the rest of the system to continue running in parallel.

Experimental Results

The proposed approach has been tested with the EURETILE and GEMSCLAIM simulators. Results using four threads and varying lookahead values were compared to sequential execution with the regular OSCI SystemC kernel. For EURETILE a speedup of 4x can be achieved while still maintaining deterministic execution and exact timing accuracy. The GEMSCLAIM simulator achieves a speedup of 3.1x with a 1% error in timing. In general, one can observe that a higher lookahead usually yields better performance, but reduces timing accuracy.