Institute for Communication Technologies and Embedded Systems

MPSoC debugging


Multi-processor Systems-on-a-Chip (MPSoCs) are proven to be the way to address performance and power consumption issues for modern embedded systems. However, the side-effects of concurrency, the heterogeneity of their components and the growing complexity of software pose new challenges on the software programming and debugging tasks. Due to their inherent non-deterministic behavior, MPSoCs are prone to concurrency bugs (e.g. data races and deadlocks).

Debuggers targeting parallel systems have further requirements than those targeting traditional sequential systems in that they need to provide a holistic system view and ease the correlation of events from different sources. Moreover, a debugger for a system bearing such complexity should provide an abstracted perspective to the user. This makes possible to give emphasis to places of the code which are relevant to the current debug tasks.


Furthermore, it is important  to maintain an unmodified execution environment when debugging parallel software. In this way, it is possible to avoid covering up concurrency bugs that highly depend on slight timing variations. Nowadays, ESL methodologies (e.g. Virtual Platforms) provide sufficient visibility, controllability, reproducibility and determinism, and are thus desired to support MPSoC debugging. In fact, these characteristics make virtual platforms more appealing and powerful to debug than the actual hardware.

Project Goals

Our research on MPSoC debugging extends state-of-the-art virtual platform technologies and proposes a novel system-wide, event-based debug methodology targeted at heterogeneous HW/SW concurrent systems. In particular, the project focuses on the following subtopics:

  • The extension and research of Virtual Platform technologies to facilitate non-intrusive event monitoring and support for MPSoC debug tasks.  
  • The design of better abstractions to represent critical system happenings for different programming models and hardware
  • The analysis of event patterns and dependencies to (semi)automatically detect and explore software failures
  • The design of an infrastructure with enough flexibility to target modern heterogeneous embedded systems


Event-based Debugging Methodology

Programmer-level events are key to abstract the complex inner workings of MPSoCs and give a comprehensive view of a concurrent system. A concurrent application can be abstracted as a set of actions directly related to communication and synchronization among concurrent entities. By observing the ordering of events in the system it is possible to spot harmful effects of processing interleavings.  

Our debug methodology is based on configurable and extensible events that makes it possible to switch between different abstraction levels of the system execution. This facilitates the debug of a complex target HW/SW ecosystem. Monitored events are derived from non-intrusive inspection of OS kernels, parallel libraries and run-time environments (RTEs). On top, bug finding algorithms or assertional techniques are then used to analyze event-based traces and detect erroneous behavior. Some of these techniques, such as the assertion-like bug-pattern descriptions, have already been proved and used in realistic embedded systems with of-the-shelf IP blocks and software.

This methodology is supported by an especial component-based debug infrastructure that grants flexibility, retargetability, scalability, SW awareness and abstraction, and builds on top of Virtual Platform technologies. This allows targeting all components in a system regardless any diverse combination of architectures and software-related elements that could appear.


The event-based debug methodology is being applied to and used with virtual platforms of industrial-strength MPSoCs for signal processing and mobile applications, including the following target processors and systems:

  • Processor architectures:
    • Tensilica (different Xtensa and Diamond variations)
    • ARM926-EJS
    • ARM Cortex A9
    • IRISC (RWTH in-house processor)
  • MPSoCs and systems:
    • Xtensa (3x) MPSoC for OFDM transceivers with in-house concurrent RTEs
    • ARM Versatile Multi-core Baseboard (4 x ARM926-EJS) with Linux
    • ARM Versatile Express (Cortex A9x4) with Linux SMP
    • Euretile

In all cases, the event-based debugger infrastructure has an acceptable overhead on the simulation performance, thus maintaining the virtual platform usable for typical software development tasks.


Luis Gabriel Murillo


Murillo, L. G., Buecs, R., Hincapie, D., Leupers, R. and Ascheid, G.: SWAT: Assertion-based Debugging of Concurrency Issues at System Level, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC)(Chiba/Tokyo, Japan), IEEE, Jan. 2015, 10.1109/ASPDAC.2015.7059074 ©2015 IEEE
Murillo, L. G., Buecs, R., Hincapie, D., Leupers, R. and Ascheid, G.: Assertion-based Debugging of Concurrency Issues in Many-core Systems across HW/SW Boundaries, in DAC Work-in-Progress Session (WIP)(San Francisco, USA), Jun. 2014
Murillo, L. G., Wawroschek, S., Castrillon, J., Leupers, R. and Ascheid, G.: Automatic Detection of Concurrency Bugs through Event Ordering Constraints, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Dresden, Germany), Mar. 2014 ©2014 IEEE
Murillo, L. G., Harnath, J., Leupers, R. and Ascheid, G.: Scalable and Retargetable Debugger Architecture for Heterogeneous MPSoCs, in System, Software, SoC and Silicon Debug Conference (S4D), Vienna, Austria, Sep. 2012, ISBN: 978-1-46732-454-0, ISSN: 2114-3684 ©2012 IEEE