Institute for Communication Technologies and Embedded Systems

Scalable and Retargetable Debugger Architecture for Heterogeneous MPSoCs

Authors:
Murillo, L. G. ,  Harnath, J. ,  Leupers, R.Ascheid, G.
Book Title:
System, Software, SoC and Silicon Debug Conference (S4D), Vienna, Austria
Date:
Sep. 2012
ISBN:
978-1-46732-454-0
ISSN:
2114-3684
Language:
English
Abstract:
The increasing degree of heterogeneity and parallelism of modern multi-processor systems on chip (MPSoCs) demand the evolution of existing software debuggers in order to keep application programming feasible. Such evolution will only be granted if next generation debuggers address key issues like abstraction, retargetability, scalability and convergence of information from different data sources. This paper presents a novel component-based, tree-aggregated debugger architecture which (i) grants flexibility and retargetability to deal with heterogeneous MPSoCs, and (ii) provides a framework to abstract complex details in order to facilitate debug of concurrency bugs. The debugger architecture is evaluated on an industrial-strength MPSoC virtual platform for mobile computing and next generation wireless communication.
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