The project is funded by the government (BMBF) and part of the ZUSE initiative („Zukunftsfähige Spezialprozessoren und Entwicklungsplattformen“).


For future tasks such as autonomous driving or Industry 4.0, ever larger amounts of data from an increasing number of sensors must be analysed in the shortest possible time using complex algorithms and artificial intelligence (AI). However, the corresponding processors must not only meet high requirements in terms of computing power, but also in terms of energy efficiency, reliability, robustness and safety, which go far beyond current possibilities. The BMBF's ZuSE projects are intended to meet the urgent need of user industries for future-proof, trustworthy processors that are tailored to their specific tasks and offer high performance.

Goals and procedure

The aim of the project is to develop a vector processor architecture for computationally intensive AI applications in driver assistance systems. Thanks to application-specific adaptations and scalability of the computing power, the processor is to be flexibly optimised for processing different sensor data. In the project, camera-, radar- and lidar-based AI applications are investigated and processors optimised for these applications are developed. A special compiler will be developed for the optimal mapping of the developed AI algorithms in a processor architecture. In addition, a broadband memory connection will ensure real-time data processing. Finally, aspects of functional security as well as logic encryption to prevent third-party intervention will be researched and implemented.

Innovations and perspectives

The flexible and scalable processor architecture is published as an open source component and offers broad industrial potential for use in the key technologies AI and the application area of autonomous driving, which are important for Germany.

Our contributions

Our institute is responsible for designing and implementing the compiler for this vector architecture. This compiler would allow the programmer to write the code for the different applications in a high-level language such as C, while still guaranteeing an efficient usage of the dedicated vector architecture.

Additionally to that, logic locking will be used (see project:Hardware Security: Secure Processor Design) to secure the integrity of the architecture and protect it from the implementation of malicious hardware Trojans.


  • Dream Chip Technologies GmbH
  • Robert Bosch GmbH
  • Cadence Design Systems GmbH
  • Technische Universität Dresden
  • Leibniz Universität Hannover (IMS)
  • RWTH Aachen University (ICE)
  • TU Kaiserslautern (EMS)