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Tool Flow and Architecture Exploration of reconfig

Tool Flow and Architecture Exploration of reconfigurable ASIPs (rASIPs)

Motivation

Future wireless communication terminals tend to become multimode, multifunctional devices. The systems have to be cognitive to changing environmental conditions as well as adaptive to variable user demands. Flexibility now is becoming more important than ever. Considering the battery-served characteristic of wireless terminals, in order to support multiple modes and access technologies in future cognitive wireless systems, the required flexibility has to be achieved with an energy efficient implementation. Reconfigurable ASIPs (rASIPs), a new variant of ASIPs where custom processor components are mapped to a Coarse-Grained Reconfigurable Architecture (CGRA), represent a very promising architectural approach to meet both flexibility and energy requirements. Designing such a rASIP provides with a huge design space and therefore, is a challenging task. The goal of this project is to build up tool flow and use it for design space exploration and implementation of rASIPs.
 

Tool Flow

The integration of the tool flow with a commercial ADL-driven processor design framework is captured in the following figure. The software tool suite as well as the processor RTL description are automatically generated from the extended ADL description. The CGRA description is conceived as a part of the ADL LISA. For RTL implementation, recent advances in LISA-based tools also allow partitioning of the processor datapath to indicate if some part is going to be synthesized on to the CGRA. The partitioning results into a DFG description (of processor's partial datapath), which is fed directly as input to the CGRA synthesis tools (mapping, placement and routing tools). The CGRA synthesis flow generates configuration bitstream, which can be simulated on the HDL implementation of the CGRA. The simulation can be done stand-alone or together with the processor.

 

Architecture Exploration

The huge design space of rASIP (partly captured in the following figure) mainly comes from various design decisions on ASIP core architecture, reconfigurable block and the interface between them. In order to gain experience in the architectural development of rASIPs, which is a fairly new research topic, complex case studies need to be developed. Given the interest and experience of the institute in the domain of physical layer processing, the rASIP approach will be applied to critical algorithms for flexible receivers. One relevant research area for flexible receivers is MIMO de-mapping. rASIP can be used to implement a multi-mode MIMO detector supporting multiple de-mapping algorithms for multiple wireless communication standards.
 

Contact

Xiaolin Chen

Publications

Chattopadhyay, A.: Ingredients of Adaptability: A Survey of Reconfigurable Processors, in VLSI Design(Hindawi), p. 18, 2013, 10.1155/2013/683615
Chen, X., Minwegen, A., Hassan, Y., Kammler, D., Li, S., Kempf, T., Chattopadhyay, A. and Ascheid, G.: FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection using reconfigurable ASIP, in The 20th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, pp. 69-76, Apr. 2012, ISBN: 978-0-76954-699-5, 10.1109/FCCM.2012.22 ©2012 IEEE
Chattopadhyay, A., Leupers, R., Meyr, H. and Ascheid, G.: Language-driven Exploration and Implementation of Partially Re-configurable ASIPs, Springer, Dec. 2008, ISBN: 978-1-40209-296-1
Karuri, K., Chattopadhyay, A., Chen, X., Kammler, D., Hao, L., Leupers, R., Meyr, H. and Ascheid, G.: A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors, in (IEEE VLSI), Vol. 16, No. 10, pp. 1281--1294, Oct. 2008
Chattopadhyay, A., Ishebabi, H., Chen, X., Rákossy, Z. E., Karuri, K., Kammler, D., Leupers, R., Ascheid, G. and Meyr, H.: Pre- and postfabrication Architecture Exploration for Partially Reconfigurable VLIW Processors, in (ACM TECS), Vol. 7, No. 4, pp. 40:1--40:31, Aug. 2008
Chattopadhyay, A., Meyr, H. and Leupers, R.: LISA: A Uniform ADL for Embedded Processor Modelling, Implementation and Software Toolsuite Generation , in Processor Description Languages ,p.p.95-130, Jun. 2008, ISBN: 978-0-12374-287-2
Chattopadhyay, A., Chen, X., Ishebabi, H., Leupers, R., Ascheid, G. and Meyr, H.: High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures, in Proceedings of the conference on Design, Automation and Test in Europe(Munich, Germany), in Proceedings of the conference on Design, Automation and Test in Europe(Munich, Germany), Mar. 2008
Chattopadhyay, A.: Language-driven Exploration and Implementation of Partially re-configurable ASIPs (rASIPs), Ph. D. Dissertation RWTH Aachen University, 2008
Chattopadhyay, A., Ahmed, W., Karuri, K., Kammler, D., Leupers, R., Ascheid, G. and Meyr, H.: Design Space Exploration of Partially Re-configurable Embedded Processors, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Nice, France), pp. 319--324, Apr. 2007
Chattopadhyay, A., Kammler, D., Zhang, D., Ascheid, G., Leupers, R. and Meyr, H.: Specification-driven Exploration and Implementation of Partially Re-configurable Processors, in Proceedings of the Global Signal Processing Expo and Conference (GSPx)(Santa Clara, California, USA), Oct. 2006
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