Sie verwenden einen Browser, in dem JavaScript deaktiviert ist. Dadurch wird verhindert, dass Sie die volle Funktionalität dieser Webseite nutzen können. Zur Navigation müssen Sie daher die Sitemap nutzen.

You are currently using a browser with deactivated JavaScript. There you can't use all the features of this website. In order to navigate the site, please use the Sitemap .

A Novel Reduced-Complexity Soft-Input Soft-Output MMSE MIMO Detector: Algorithm and Efficient VLSI Architecture

Authors:: Auras, D. , Leupers, R. , Ascheid, G.
Book Title:: Proceedings of the 2014 IEEE International Conference on Communications (ICC)
Publisher:: IEEE
Pages:: p.p. 4722-4728
Date:: Jun. 2014
DOI:: 10.1109/ICC.2014.6884067
Language:: English
Abstract:: A novel reduced-complexity soft-input soft-output minimum mean square error detection algorithm for MIMO systems together with an area-throughput efficient VLSI architecture is described. A detailed comparison to related work is presented. The proposed VLSI architecture of the novel algorithm represents — to the best of our knowledge — the most areathroughput efficient SISO MIMO detector ASIC reported so far, being 2.3x more efficient than its best competitor. It achieves a throughput of up to 923 Mbit/s and occupies down to half of the competitor’s area while sustaining the IEEE 802.11n standard’s peak data rate.
Download:: BibTeX
Copyright © by IEEE AurasICC2014.pdf: © 2024 IEEE.Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.