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Buffer Allocation based On-Chip Memory Optimization for Many-Core Platforms

Authors:: Odendahl, M. , Goens, A. , Leupers, R. , Ascheid, G. , Henriksson, T.
Book Title:: Fifth International Workshop on Parallel Computing and Optimization
Pages:: p.p. 1119-1124
Date:: May. 2015
ISBN:: 978-1-46737-684-6
DOI:: 10.1109/IPDPSW.2015.67
Language:: English
Abstract:: The problemof finding an optimal allocation of logical data buffers to memory has emerged as a new research challenge due to the increased complexity of applications and new emerging Dynamic RAM (DRAM) interface technologies. This new opportunity of a large off-chip memory accessible by an ample bandwidth allows to reduce the on-chip Static RAM (SRAM) significantly and save production cost of future many-core platforms. We thus propose changes to an existing work that allows to uniformly reduce the on-chip memory size for a given application. We additionally introduce a novel linear programming model to automatically generate all necessary on-chip memory sizes for a given application based on an optimal allocation of data buffers. An extension allows to further reduce the required onchip memory in multi-application scenarios. We conduct a case study to validate all our models and show the applicability of our approach.
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