Institute for Communication Technologies and Embedded Systems

SuperSim - A new technique for simulation of programmable DSP architectures

Zivojnovic, V. ,  Pees, S. ,  Schläger, C. ,  Weber, R. ,  Meyr, H.
Book Title:
Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)
p.p. 1748-1763
Oct. 1995
This paper presents a technique for simulating DSP processors based on the principle of compiled simulation. Unlike existing, commercially available instruction set simulators for DSP processors, which are of interpretive character, the proposed technique performs instruction decoding and simulation scheduling at compile time. The technique offers up to three orders of magnitude faster simulation. The high speed allows the user to explore algorithms and hardware/software trade-offs before any hardware implementation. Moreover, the user can tailor the compiled simulation to trade speed for more accuracy. In this paper, the sources of the immense speedup are analyzed and the realization of the simulation compiler is presented.

Copyright © by ICE
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.