Recently, it has become possible to place multiple processors and several busses on a single chip (System-on-Chip). In order to check very early in the design flow if the entire design is working correctly and if the performance is high enough, we absolutely need to efficiently simulate the whole system. The LISATek tools-suite allows automatically generating efficient simulators for arbitrary processors (mostly tailored for the respective application). Its input is an abstract processor model written in the LISA language. Analogously, the CoWare BusCompiler can generate an efficient bus simulator, taking an abstract bus model description as input.
For the complete SoC simulator, we need to couple the automatically generated module simulators. We want to be able to automatically combine arbitrary bus protocols with arbitrary processor architectures. Thus, respective code generators have to be developed.