Institute for Communication Technologies and Embedded Systems


Digital Video Broadcasting

Algorithm Design for the DVB Carrier and Timing Synchronizer

This page briefly describes the steps that lead to the development of the synchronization algorithms for the DVB chipset developed in conjunction with an industrial partner. Speaking techncally, the goal of the synchronizer is to provide samples of the transmitted symbols perturbed by additive white gaussian noise, only. Hence other perturbations of the signal, like frequency offsets or perturbations from the analog frontend have to be removed using suitable algorithms, secondly the power of the noise shall be kept as small as possible.


System parameters

Eb/N0 3.4 ... 6dB
frequency offsets about 10%
symbol rates 20-44Ms/s
channel coding Viterbi + Reed Solomon
Viterbi Code Rates 1/2 ... 7/8
Acquisition Times about 50ms


Algorithm Design

Algorithm Design started with modeling the interfaces to the analog units and with claryfying the target SNR loss that should be met. This step especially took into account A/D quantization, AGC models and a model of the analog prefilter. What we also did was to outline the acquisition procedure and to specify important parameters for variable symbol rate synchronization

Following these steps, we started to develop algorithms suitable for variable symbol rate timing synchronization which eventually lead to devising suitable feedback synchronizer structures. Secondly, the algorithms for carrier synchronization were developed using the same methodology. We decided to use well-known feedback synchronization algorithms based on digital phase locked loops. These structures were tested in a floating point environment ignoring degradations coming from quantization and nonlinear distortions from the frontend. In this step, a 'coarse' model of the channel decoder helped to assess the BER degradations coming from the nonideal synchronization.


After having determined the algorithmic structure of the synchronizer, any signal that was used on the chip had to be quantized in order to comply with the finite (as it will become an ASIC, very finite) wordlength available for any signal. During this step of the design, any effect of the frontend, as well as a much refinded model of the (inner) channel (Viterbi decoder was taken into account. The degradation was found to match the requirements stated in the beginning of the project.



Meik Dörpinghaus