Algorithm Design started with modeling the interfaces to the analog units and with claryfying the target SNR loss that should be met. This step especially took into account A/D quantization, AGC models and a model of the analog prefilter. What we also did was to outline the acquisition procedure and to specify important parameters for variable symbol rate synchronization
Following these steps, we started to develop algorithms suitable for variable symbol rate timing synchronization which eventually lead to devising suitable feedback synchronizer structures. Secondly, the algorithms for carrier synchronization were developed using the same methodology. We decided to use well-known feedback synchronization algorithms based on digital phase locked loops. These structures were tested in a floating point environment ignoring degradations coming from quantization and nonlinear distortions from the frontend. In this step, a 'coarse' model of the channel decoder helped to assess the BER degradations coming from the nonideal synchronization.