The applications in the embedded domain such as wireless communication and multimedia are nowadays very complex. To meet the high application requirements regarding latency and throughput, systems with high computational performance are demanded. This calls for multi-processor systems-on-chip (MPSoCs).
The performance of an MPSoC is largely determined by the contained processor cores and hardware accelerators, but for large-scale systems the communication architecture between the different components is also of vital importance. If it is not properly designed, it could be the bottleneck of the system. Furthermore, the power and energy consumption of all components is also important and has to be respected during the development of an MPSoC. Trade-offs have to be made between the power consumption and the performance when choosing processor cores and designing the communication architectures.
Due to the extremely slow speed the traditional power estimation techniques at register transfer level (RTL) or after place&route are not suitable anymore for performing efficient design space explorations for large systems. However, this is very important for development of competitive products and keeping the time-to-market short. Therefore, high-level power estimation on Electronic System Level (ESL) is desired, as it is able to guide the designer to efficiently draw design decisions at an early stage.