Power efficiency is increasingly important for today's highly complex integrated circuits, especially for mobile and consumer applications. For mobile devices the battery lifetime can be enhanced using low-power design techniques. For consumer applications like DVB-T packaging and cooling of the integrated circuit significantly add up to the sensitive overall cost per unit. This is the reason why power consumption is an important design parameter in the ICORE design methodology.
 

ICORE is initially based on a mainly conventional DSP instruction set of a typical load/store Harvard-DSP architecture. This instruction set includes instructions for arithmetic and logical operations, data moves, and program flow control. It could be a subset of any micro-controller or DSP instruction set without special instructions like e. g. rounding, division, normalization, bit test, and loop operations. With these basic instructions an initial assembler version of the algorithm is created. This implementation at this stage is typically not the optimum solution with respect to execution time and power consumption and may violate any
given time constraints.
 

One result of this step is the cycle count for the implemented algorithm. Together with the system clock frequency this results in the execution time for the profiled task. Logic synthesis of the corresponding HDL-description of the processor for the target technology has to check if this architecture is feasible for a given clock speed. If time constraints for a profiled task are violated, architectural enhancements corresponding to instruction set modifications have to be performed to accelerate this task. Here, a coprocessor for a runtime critical task can be added, if an ISA adaptation fails to satisfy the constraints.

If all time constraints are fulfilled, additional optimizations can be introduced to increase power efficiency. It is often impossible to separate performance optimization from energy optimization, because ISA performance improvements typically also reduce the overhead energy.

Generally speaking the following power optimization steps are applicable:

• optimum partitioning on the system level
• sleep-/doze modes of the processor
• local/global clock gating
• blocking logic to suppress wasteful logic activity
• data-path optimization using application specific instructions and functional units
• high instruction coding density / application specific instruction encoding
• software optimization
• ...

For ICORE, all the above mentioned techniques have been applied jointly. As a result it was possible to reduce the ICORE energy consumption by about one order of magnitude.

• ICORE
• Architecture
• Methodology