Designing an ASIP for Retinex Image and Video Processing

Image enhancement processes play an important role in consumer electronics today. The Retinex class of algorithms aims at improving the visual representation of scenes taking into account the human physiology. The Retinex theory was introduced by Edwin H. Land in 1964 [1] based on the observation that objects look almost the same in different illumination scenarios. In the Retinex theory, image pixels are expressed by two factors, the ambient illumination and the reflectance. By processing illumination and reflectance independently with the aid of non-linear transformations, visual improvements of images or videos can be achieved that enhance the details of dark parts of the scene without overexposing the bright parts.

One challenge of applying a Retinex filter on an image is the high computational complexity which makes pure software implementations on digital signal processors hard to realize.  Especially in the embedded domain, where real-time constraints and energy limitations cause high demands, efficient design solutions are required. Furthermore, Retinex algorithms depend on the target scenario (like medical, automotive, consumer, etc.). Therefore, a flexible, i.e. programmable, solution. Application-specific instruction-set processors (ASIPs) offer exactly this desired trade-off between performance and flexibility. Goal of this project is thus to develop an ASIP for Retinex processing by means of the architecture description language LISA.

The project started in March 2005 as a cooperation between the ISS and the DIIEIT from Pisa University within the European Newcom project. Within this project, one PhD student from Pisa joint the ASIP team in Aachen in order to learn the concepts and use of the LISA technology. The LISA technology enabled to conceptualize, implement, verify and prototype the Retinex ASIP core within a period of two month only. The FPGA-based demonstrator has been presented at various conferences and other occasions around the world including Dresden (Germany), Lausanne (Switzerland), Tottori (Japan), and Paris (France).
Conceptual and architectural details of the Retinex ASIP can be found in the international publications listed below.
 

[1] E. H. Land, "The Retinex," American Scientist, vol. 52, no. 2, pp. 247–264, 1964.

Contact

David Kammler, Ernst Martin Witte, Oliver Schliebusch

Cooperation partner

Dipartimento di Ingegneria dell'Informazione (DIIEIT), University of Pisa

Publications

Saponara, S., Fanucci, L., Marsi, S., Ramponi, G., Kammler, D. and Witte, E. M.: Application-Specific Instruction-Set Processor for Retinex-Like Image and Video Processing, In (IEEE TCAS II) Vol. 54 , p.p. 596--600 , No. 7 Jul/2007


Saponara, S., Fanucci, L., Marsi, S., Ramponi, G., Witte, E. M. and Kammler, D.: Design of Application Specific Instruction-Set Processor for Image and Video Filtering, in Proceedings of European Signal Processing Conference (EUSIPCO) , (Florence, Italy) Sep/2006


Fanucci, L., Cassiano, M., Saponara, S., Kammler, D., Witte, E. M., Schliebusch, O., Ascheid, G., Leupers, R. and Meyr, H.: ASIP Design and Synthesis for Non Linear Filtering in Image Processing, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE) , 2 , p.p. 233--238 , (Munich, Germany) Mar/2006