DAB

In this Viterbi Decoder at each data clock cycle 64 node equations have to be computed (each single computation requiring about 5 DSP instructions). The required data rate of 3 Mbit/s (``full-rate') therefore leads to 3*64*5 MOps/sec = 1 GOps/sec. Due to this high amount of equivalent DSP operations per second a standard programable DSP solution using an off-the-shelf DSP chip was impossible and a special ASIC (application specific integrated circuit) had to be developed.

Several VLSI architectures for Viterbi decoders are known from literature. But since the required data rate was higher than the data rate provided by node-serial architectures (they use a single processing element) and lower than that provided by traditional node-parallel architectures (N=64 Processing elements) a special architecture has been developed for an area-efficient solution. This architecture uses 8 processing elements. Using 8 processing elements to compute the 64 node equations saves silicon area but requires a somewhat complex scheduling scheme. The computation of the required schedules for this area-efficient class of Viterbi decoder architectures for medium speed may be found in the following paper:
"S. J. Bitterlich, H. Meyr, Efficient Scalable Architectures for Viterbi Decoders"
(published in Proceedings of the 1993 Conference on Application Specific Array Processors, Venice, Italy).

A comparision of the new Viterbi decoder architectures down to the VLSI layout level (for 1.0um CMOS semi-custom implementations) may be found in the paper:
"S. J. Bitterlich, H. Meyr, Area-Efficient Viterbi Decoder Macros"
(published in Proceedings of the 1994 European Solid-State Circuits Conference (ESSCIRC'94), Ulm, Germany).

We used VHDL (Very High-level Hardware Description Language) to describe the VLSI-architecture. A state-of-the-art logic synthesis tool (Synopsys Design Compiler) has been used to synthesize a netlist for a CMOS composite gate array technology ( we also offer an VHDL-based ASIC-design course ; please refer to our lectures section [GERMAN])

The implementation has been verified by COSSAP-VHDL co-simulation: The system simulator COSSAP was used to generate a simulated noisy received signal and provided a perfect (floating-point) Viterbi Decoder (``golden device'') from its library. Simultaneously a VHDL simulator was used to execute the developed VHDL description of the DAB Viterbi Decoder. By (automatic) comparision of both results we verified the correctness of the developed VHDL code. In addition, our industry partners performed a gate-level simulation of the synthesized netlist to verify the synthesis process and the operating frequency of the design.

The details of the implemented ASIC and the design methodologies are presented in the paper (IN GERMAN): "S. J. Bitterlich, W. Brugger, G. Bergmann, H. Meyr, Ein Viterbi Decoder fuer den digitalen Rundfunk" (7. ITG Fachtagung Mikroelektronik fuer die Informationstechnik, Chemnitz, Germany, March 1996)

We finished our work at the DAB Viterbi Decoder in Mid-1995. Currently we are implementing several other parts of the DAB receiver:

• The frequency de-interleaver
• A data block reformater / logical channel extractor
• The time de-interleaver