Institute for Communication Technologies and Embedded Systems

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Design and Analysis of Layered Coarse-Grained Reconfigurable Architecture

Authors:
Rákossy, Z. E. ,  Naphade, T. ,  Chattopadhyay, A.
Book Title:
International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Address:
Cancun, Mexico
Date:
Dec. 2012
Language:
English
Abstract:
Coarse-grained reconfigurable architectures
(CGRAs) represent an important class of programmable
accelerators with a significant performance advantage for
data-driven, systolic algorithms. In this paper, we present a
novel CGRA where data access, data transport and execution
are separately layered into dedicated, independent structures.
The proposed architecture concept allows for independent
control and optimization on each layer to address the storage
access bottleneck, faced by state-of-the-art CGRAs. The
architecture is programmable and the implementation is
derived from a high-level language specification, allowing fast
design exploration, debugging and simulation. Up to 50%
run-time performance improvement and 5× area-time-energy
product gain of the layered CGRA over a non-layered one
is demonstrated with 2 case studies from demanding linear
algebra applications.

Keywords -
Coarse-Grained Reconfigurable Architecture(CGRA);
LU decomposition;
Matrix Multiplication;
Layered Architecture;
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