Sie verwenden einen Browser, in dem JavaScript deaktiviert ist. Dadurch wird verhindert, dass Sie die volle Funktionalität dieser Webseite nutzen können. Zur Navigation müssen Sie daher die Sitemap nutzen.

You are currently using a browser with deactivated JavaScript. There you can't use all the features of this website. In order to navigate the site, please use the Sitemap .

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip

Authors:: Joseph, J. M. , Wrieden, S. , Blochwitz, C. , García-Ortiz, A. , Pionteck, T.
Book Title:: 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Pages:: p.p. 1-8
Date:: 2016
DOI:: 10.1109/ReCoSoC.2016.7533908
Language:: English
Abstract:: We present a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of interwoven parameters of the communication infrastructure and characteristics of the manufacturing technologies. Thus, simultaneous evaluation of multiple design metrics is mandatory. Our simulation environment consists of three parts. First, it comprises a NoC simulator that supports a multitude of different manufacturing technologies, router architectures, and network topologies within a single design. As a key feature, the NoC and technologies parameters per chip layer are fully configurable during simulation runtime permitting flexible and fast evaluation. Second, a central reporting tool facilitates system analysis on different abstraction levels. Third, the evolution tool provides various synthetic and real-world based benchmarks. Thus, our tool allows for an incremental approach to systematically explore the A-3D-NoC's design space.
Download:: BibTeX